Method and apparatus for a brown out detector

Patent metadata

Field	Value
Publication number	US-9634653-B2
Application number	US-201414587300-A
Country	US
Kind code	B2
Filing date	Dec 31, 2014
Priority date	Dec 11, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

The disclosure provides a detector that includes a pre-charge circuit. The pre-charge circuit receives a supply voltage. A pre-charged comparator is coupled to the pre-charge circuit and receives the supply voltage. The pre-charged comparator generates a transition signal at a transition node. A slope of the transition signal is greater than a slope of the supply voltage. A first diode connected transistor receives the supply voltage. A first capacitor is coupled to the first diode connected transistor. An inverter is coupled to the first diode connected transistor and generates an enable signal when the supply voltage is below a threshold voltage.

First claim

What is claimed is:

1. A detector comprising:
a pre-charge circuit configured to receive a supply voltage;
a pre-charged comparator coupled to the pre-charge circuit and configured to receive the supply voltage and configured to generate a transition signal at a transition node, wherein a slope of the transition signal is greater than a slope of the supply voltage;
a diode connected transistor configured to receive the supply voltage;
a capacitor coupled to the diode connected transistor; and
an inverter coupled to the diode connected transistor, the inverter having an input coupled to the transition node, and being configured to generate an enable signal when the supply voltage is below a threshold voltage.

2. The detector of claim 1 , wherein the capacitor is a first capacitor, wherein the diode connected transistor is a first diode connected transistor, and wherein the pre-charged comparator comprises:
a second capacitor configured to receive the supply voltage;
a second diode connected transistor coupled to the second capacitor;
a third capacitor coupled to the pre-charge circuit at the transition node; and
a switch coupled between the second capacitor and the transition node.

3. The detector of claim 2 , wherein the second diode connected transistor, the third capacitor and the switch are coupled to a ground terminal.

4. The detector of claim 2 , wherein a capacitance of the second capacitor is greater than a capacitance of the third capacitor.

5. The detector of claim 2 , wherein the second capacitor is charged to the supply voltage, and the third capacitor is charged to the supply voltage through the pre-charge circuit.

6. The detector of claim 2 , wherein when the supply voltage is below the threshold voltage, the second diode connected transistor is reverse biased and the switch is activated.

7. The detector of claim 6 , wherein when the switch is activated, the third capacitor is discharged through the second capacitor such that the transition signal deactivates an NMOS transistor.

8. The detector of claim 1 , wherein the inverter comprises:
a PMOS transistor whose gate terminal is configured to receive the supply voltage and whose source terminal is coupled to the capacitor; and
an NMOS transistor whose gate terminal is coupled to the transition node and whose source terminal is coupled to the ground terminal, wherein a drain terminal of the PMOS transistor is coupled to a drain terminal of the NMOS transistor to generate the enable signal.

9. The detector of claim 1 , wherein the diode connected transistor is a PMOS transistor whose gate terminal is coupled to a drain terminal.

10. The detector of claim 1 , wherein the pre-charge circuit is at least one of a mono-shot trigger circuit and a weak pull-up circuit.

11. A method comprising:
providing a supply voltage;
generating a transition signal when the supply voltage is below a threshold voltage, wherein a slope of the transition signal is greater than a slope of the supply voltage;
deactivating an NMOS transistor by the transition signal; and
activating a PMOS transistor to generate an enable signal when the supply voltage is below the threshold voltage, a drain terminal of the PMOS transistor being coupled to a drain terminal of the NMOS transistor.

12. The method of claim 11 further comprising charging a first capacitor, a second capacitor and a third capacitor to the supply voltage.

13. The method of claim 11 further comprising reverse biasing a diode connected transistor and activating a switch, when the supply voltage is below the threshold voltage.

14. The method of claim 13 further comprising discharging the third capacitor through the second capacitor to generate the transition signal when the switch is activated.

15. The method of claim 11 further comprising activating the PMOS transistor by a capacitor when the supply voltage is below the threshold voltage.

16. A device comprising
an integrated circuit;
a power on reset (POR) circuit coupled to the integrated circuit; and
a detector coupled to the POR circuit, the detector comprising:
a pre-charge circuit configured to receive a supply voltage;
a pre-charged comparator coupled to the pre-charge circuit and configured to receive the supply voltage and configured to generate a transition signal at a transition node, wherein a slope of the transition signal is greater than a slope of the supply voltage;
a diode connected transistor configured to receive the supply voltage;
a capacitor coupled to the diode connected transistor; and
an inverter coupled to the diode connected transistor, the inverter having an input coupled to the transition node, and being configured to generate an enable signal when the supply voltage is below a threshold voltage.

17. The device of claim 16 , wherein the capacitor is a first capacitor, wherein the diode connected transistor is a first diode connected transistor, and wherein the pre-charged comparator comprises:
a second capacitor configured to receive the supply voltage;
a second diode connected transistor coupled to the second capacitor;
a third capacitor coupled to the pre-charge circuit at the transition node; and
a switch coupled between the second capacitor and the transition node.

18. The device of claim 17 , wherein the second capacitor is charged to the supply voltage, and the third capacitor is charged to the supply voltage through the pre-charge circuit.

19. The device of claim 17 , wherein:
when the supply voltage is below the threshold voltage, the second diode connected transistor is reverse biased and the switch is activated; and
when the switch is activated, the third capacitor is discharged through the second capacitor such that the transition signal deactivates an NMOS transistor.

20. The device of claim 16 , wherein the inverter comprises:
a PMOS transistor whose gate terminal is configured to receive the supply voltage and whose source terminal is coupled to the capacitor; and
an NMOS transistor whose gate terminal is coupled to the transition node and whose source terminal is coupled to a ground terminal, wherein a drain terminal of the PMOS transistor is coupled to a drain terminal of the NMOS transistor to generate the enable signal.

Assignees

• Texas Instruments Inc

Inventors

• Subramanian Anand
• Narayan Subramanian J

Classifications

• H03K17/223 Primary

  in field-effect transistor switches · CPC title

• H03K5/2472 Primary

  using field effect transistors (H03K5/2436 takes precedence) · CPC title

• H03K5/19

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title