Switching mode power supply and the controller and the method thereof

Patent metadata

Field	Value
Publication number	US-9634572-B2
Application number	US-201514859070-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	Sep 19, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A switching mode power supply with resonant technology. The switching mode power supply current uses current polarity evaluation to avoid capacitive mode by triggering the capacitive protection if the evaluation indicates that the system will enter capacitive mode.

First claim

We claim:

1. A controller used in a switching mode power supply, the switching mode power supply having a power stage and a resonant tank, the power stage including a first power switch and a second power switch coupled in series, and the resonant tank including a resonant inductor and a resonant capacitor, the controller comprising:
a polarity evaluating circuit, configured to receive a clock signal and a current sense signal indicative of a current flowing through the resonant inductor, wherein the polarity evaluating circuit generates a capacitive evaluated signal based on the current sense signal and the clock signal;
a control and logic circuit, configured to receive the clock signal and the capacitive evaluated signal, to generate a first logical signal and a second logical signal;
a logic delay circuit, coupled to the control and logic circuit to receive the first logical signal and the second logical signal, wherein the logic delay circuit generates a first logical delayed signal and a second logical delayed signal based on the first logical signal and the second logical signal; and
a driven circuit, coupled to the logical delay circuit to receive the first logical delayed signal and the second logical delayed signal to generate a first driving signal and a second driving signal, to control the first power switch and the second power switch, respectively.

2. The controller of claim 1 , wherein the polarity evaluating circuit comprises:
a positive comparator, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the current sense signal, the second input terminal is configured to receive a first threshold, and wherein the positive comparator generates a positive comparison signal based on the current sense signal and the first threshold;
a negative comparator, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the current sense signal, the second input terminal is configured to receive a second threshold, and wherein the negative comparator generates a negative comparison signal based on the current sense signal and the second threshold;
a first D flip flop, having a trigger input terminal, a clock input terminal, a reset terminal and an output terminal, wherein the trigger input terminal is coupled to the positive comparator to receive the positive comparison signal, the clock input terminal is configured to receive an inverted clock signal complementary to the clock signal, and the reset terminal is configured to receive the clock signal, wherein based on the positive comparison signal and the rising edge of the inverted clock signal, the first D flip flop generates a positive evaluated signal at the output terminal, and resets the positive evaluated signal at the rising edge of the clock signal;
a second D flip flop, having a trigger input terminal, a clock input terminal, a reset terminal and an output terminal, wherein the trigger input terminal is coupled to the negative comparator to receive the negative comparison signal, the clock input terminal is configured to receive the clock signal, and the reset terminal is configured to receive the inverted clock signal, wherein based on the negative comparison signal and the rising edge of the clock signal, the second D flip flop generates a negative evaluated signal at the output terminal, and resets the negative evaluated signal at the rising edge of the inverted clock signal; and
a logical OR circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the positive evaluated signal, the second input terminal is configured to receive the negative evaluated signal, wherein based on the positive evaluated signal and the negative evaluated signal, the logical OR circuit generates the capacitive evaluated signal at the output terminal.

3. The controller of claim 1 , wherein the polarity evaluating circuit evaluates the current polarity of the current sense signal at the falling edges of the first logical signal and the second logical signal to generate the capacitive evaluated signal.

4. The controller of claim 1 , wherein the control and logic circuit comprises:
a timer, configured to provide a timing signal;
a first logical AND circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the timer to receive the timing signal, the second input terminal is configured to receive the capacitive evaluated signal, wherein based on the timing signal and the capacitive evaluated signal, the first logical AND circuit generates a capacitive reset signal;
a first logical OR circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first logical AND circuit to receive the capacitive reset signal, the second input terminal is configured to receive a first dead time setting signal, wherein based on the capacitive reset signal and the first dead time setting signal, the first logical OR circuit generates a first reset signal at the output terminal;
a second logical OR circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first logical AND circuit to receive the capacitive reset signal, the second input terminal is configured to receive the second dead time setting signal, wherein based on the capacitive reset signal and the second dead time setting signal, the second logical OR circuit generates a second reset signal at the output terminal;
a first RS flip flop, having a set input terminal, a reset input terminal and an output terminal, wherein the set input terminal is configured to receive the clock signal, the reset input terminal is coupled to the first logical OR circuit to receive the first reset signal, wherein based on the clock signal and the first reset signal, the first RS flip flop generates the first dead time signal at the output terminal;
a second RS flip flop, having a set input terminal, a reset input terminal and an output terminal, wherein the set input terminal is configured to receive the inverted clock signal, the reset input terminal is coupled to the second logical OR circuit to receive the second reset signal, wherein based on the inverted clock signal and the second reset signal, the second RS flip flop generates a second dead time signal at the output terminal;
a logical NOR circuit, having a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal is coupled to the first RS flip flop to receive the first dead time signal, the second input terminal is coupled to the second RS flip flop to receive the second dead time signal, wherein based on the first dead time signal and the second dead time signal, the logical NOR circuit generates a dead time signal at the first output terminal and a non-dead time signal at the second output terminal;
a second logical AND circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the logical NOR circuit to receive the non-dead time signal, the second input terminal is configured to receive the clock signal, wherein based on the non-dead time signal and the clock signal, the second logical AND circuit generates the first logical signal at the output terminal; and
a third logical AND circuit, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the logical NOR circuit to receive the non-dead time signal, the second input termin

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Jin Yiqing
• Chen Yuedong
• Lin Sicong

Classifications

• H02M1/32 Primary

  Means for protecting converters other than automatic disconnection · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• Y02B70/1433

  Cross-Sectional Technologies · mapped topic

• Y02B70/1491

  Cross-Sectional Technologies · mapped topic

• H02M3/157

  with digital control · CPC title