Charge pumping apparatus for low voltage and high efficiency operation

Patent metadata

Field	Value
Publication number	US-9634559-B2
Application number	US-201514615062-A
Country	US
Kind code	B2
Filing date	Feb 5, 2015
Priority date	Feb 7, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A charge pump (CP) that operates at low input voltage with high power conversion efficiency is disclosed. A first embodiment provides a negative CP used for controlling load switches of a voltage doubler. Using a negative CP extends the operating region below ground to relieve the power delivery limitation of the CP. A second embodiment provides a low power adaptive dead-time circuit, which has several dead-time signals having different lengths of dead-times and selects one according to the input voltage level. A low input voltage detector in the adaptive dead-time circuit is used to determine which dead-time should be used. A third embodiment provides a switching body bias used for the low input voltage CP. The switching body bias uses both forward and reverse body bias applied to the CP to minimize reverse current and maximize power transfer. The first, second, and third embodiments can be used together or independently.

First claim

The invention claimed is:

1. A charge pump circuit, comprising:
two or more unit charge pumps arranged in series, wherein each unit charge pump includes:
a first pumping capacitor,
a second pumping capacitor,
two cross-coupled NMOS switches, wherein the first pumping capacitor is coupled to the source of a first cross-coupled NMOS switch and the gate of the second cross-coupled NMOS switch, and the second pumping capacitor is coupled to the source of the second cross-coupled NMOS switch and the gate of the first cross-coupled NMOS switch, and
four PMOS switches for switching body biasing applied to the two cross-coupled NMOS switches, wherein the four PMOS switches are controlled by a pair of complementary clock signals having an adjustable dead-time based on an input voltage for the charge pump circuit, wherein the adjustable dead-time corresponds to a non-overlapping time period between a rising edge of one of the complementary clock signals and a corresponding falling edge of the other of the complementary clock signals.

2. The charge pump according to claim 1 , further comprising:
an adaptive dead-time circuit that includes dead-time circuits with different lengths of dead-times and an input voltage detector.

3. The charge pump according to claim 2 , wherein each unit charge pump doubles an input voltage of the unit charge pump by using overlapping clock signals, wherein the overlapping clock signals are generated by the adaptive dead-time circuit.

4. The charge pump according to claim 2 , wherein the adaptive dead-time circuit forwards outputs of one of the dead-time circuits with different length of dead-times to the one or more unit charge pumps.

5. The charge pump according to claim 2 , further comprising:
a switch-conductance enhancer that includes a negative charge pump and auxiliary charge pumps,
wherein the adaptive dead-time circuit forwards outputs of one of the dead-time circuits with different length of dead-times to the switch-conductance enhancer.

6. The charge pump according to claim 2 , wherein one dead-time circuit is selected by the input voltage detector according to an input voltage level of the charge pump circuit.

7. The charge pump according to claim 2 , wherein an input to the charge pump circuit is the supply voltage of the adaptive dead-time circuit.

8. The charge pump according to claim 2 , wherein:
at low input voltage levels, the input voltage detector commands the adaptive dead-time circuit with short dead-time to be selected in the adaptive dead-time circuit; and
at high input voltage levels, the input voltage detector commands the adaptive dead-time circuit with long dead-time to be selected in the adaptive dead-time circuit;
wherein a threshold voltage defines a boundary between low and high input voltage levels.

9. The charge pump according to claim 1 , further comprising:
a switch-conductance enhancer that includes a negative charge pump and auxiliary charge pumps.

10. The charge pump according to claim 9 , wherein each unit charge pump further includes:
two series switches, wherein the four PMOS switches for switching body biasing and the two series switches are controlled by signals that are generated by the switch-conductance enhancer.

11. The charge pump according to claim 9 , wherein the four PMOS switches for switching body biasing are driven by signals from the switch-conductance enhancer.

12. The charge pump according to claim 11 , wherein the signals of the switch-conductance enhancer swing between a negative voltage and an output voltage level of the charge pump circuit.

13. The charge pump according to claim 12 , wherein the negative voltage is generated by the negative charge pump.

14. The charge pump according to claim 13 , wherein the output voltage level of the charge pump circuit is generated by the auxiliary charge pumps.

15. The charge pump according to claim 1 , wherein an output of a first unit charge pump is connected to an input of a second unit charge pump, and an output of the second unit charge pump is connected to an input of a third unit charge pump.

16. A charge pump circuit, comprising:
a first pumping capacitor;
a second pumping capacitor;
two cross-coupled NMOS switches, wherein the first pumping capacitor is coupled to the source of a first cross-coupled NMOS switch and the gate of the second cross-coupled NMOS switch, and the second pumping capacitor is coupled to the source of the second cross-coupled NMOS switch and the gate of the first cross-coupled NMOS switch; and
four PMOS switches for switching body biasing applied to the two cross-coupled NMOS switches, wherein the four PMOS switches are controlled by a pair of complementary clock signals having an adjustable dead-time based on an input voltage for the charge pump circuit, wherein the adjustable dead-time corresponds to a non-overlapping time period between a rising edge of one of the complementary clock signals and a corresponding falling edge of the other of the complementary clock signals.

17. The charge pump circuit according to claim 16 , wherein the charge pump circuit is connected to an adaptive dead-time circuit that includes dead-time circuits with different lengths of dead-times and an input voltage detector.

18. The charge pump circuit according to claim 17 , wherein the charge pump circuit doubles an input voltage of the charge pump circuit by using overlapping clock signals, wherein the overlapping clock signals are generated by the adaptive dead-time circuit.

19. The charge pump circuit according to claim 17 , wherein the charge pump circuit is further connected to a switch-conductance enhancer that includes a negative charge pump and auxiliary charge pumps, wherein the adaptive dead-time circuit forwards outputs of one of the dead-time circuits with different length of dead-times to the switch-conductance enhancer.

20. The charge pump circuit according to claim 19 , wherein the four PMOS switches for switching body biasing are driven by signals from the switch-conductance enhancer.

21. An adaptive dead-time circuit, comprising:
a short dead-time circuit;
a long dead-time circuit, wherein a dead-time of the long dead-time circuit is longer than a dead-time of the short dead-time circuit;
an input voltage detector coupled to an input voltage level of a charge pump circuit; and
a multiplexer configured to select between an output of the short dead-time circuit and an output of the long dead-time circuit based on a signal from the input voltage detector to determine an output of the adaptive dead-time circuit;
wherein the output of the adaptive dead-time circuit provides an adjustable dead-time for a pair of complementary clock signals, wherein the adjustable dead-time corresponds to a non-overlapping time period between a rising edge of one of the complementary clock signals and a corresponding falling edge of the other of the complementary clock signals.

22. The adaptive dead-time circuit according to claim 21 , wherein the output of the adaptive dead-time circuit is forwarded to the charge pump circuit, wherein the charge pump circuit includes one or more unit charge pumps.

23. The adaptive dead-time circuit according to claim 22 , wherein each unit charge pump doubles an input voltage of the unit charge pump by using overlapping clock signals, wherein the overlapping clock signals are generated by the adaptive dead-time circuit.

24. The adaptive dead-time circuit accor

Assignees

• Univ Hong Kong Science & Tech

Inventors

• Kim Jungmoon
• Mok Kwok Tai Philip
• Kim Chulwoo

Classifications

• H02M2003/078

  Electricity · mapped topic

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/078

  with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters · CPC title