Semiconductor structure and method of forming the same

Patent metadata

Field	Value
Publication number	US-9634243-B1
Application number	US-201514953238-A
Country	US
Kind code	B1
Filing date	Nov 27, 2015
Priority date	Nov 27, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a first N th metal line of an N th metal layer, a magnetic tunneling junction (MTJ) over first N th metal line, and a first (N+1) th metal via of an (N+1) th metal layer, the first (N+1) th metal via being disposed over the MTJ layer. N is an integer greater than or equal to 1. A method of manufacturing the semiconductor structure is also disclosed.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a logic region;
a memory region adjacent to the logic region, the memory region comprises:
a first N th metal line of an N th metal layer;
a magnetic tunneling junction (MTJ) over first N th metal line; and
a first (N+1) th metal via of an (N+1) th metal layer, the first (N+1) th metal via being disposed over the MTJ layer,

wherein N is an integer greater than or equal to 1.

2. The semiconductor structure of claim 1 , wherein the logic region comprises:
a second N th metal line of the N th metal layer;
a first N th metal via of the N th metal layer, the first N th metal via being disposed over the second N th metal line;
a first (N+1) th metal line of the (N+1) th metal layer, the first (N+1) th metal line being disposed over the first N th metal via; and
a second (N+1) th metal via of the (N+1) th metal layer, the second (N+1) th metal via being disposed over the first (N+1) th metal line.

3. The semiconductor structure of claim 2 , wherein a sum of a thickness of the first N th metal via and a thickness of the first (N+1) th metal line in the logic region is essentially the same as a thickness of the MTJ in the memory region.

4. The semiconductor structure of claim 2 , wherein the sum of a thickness of the first N th metal via and a thickness of the first (N+1) th metal line in the logic region is smaller than about 1200 Å.

5. The semiconductor structure of claim 1 , wherein the MTJ comprises a top electrode electrically coupling to the first (N+1) th metal via.

6. The semiconductor structure of claim 1 , wherein the MTJ comprises a bottom electrode electrically coupling to the first N th metal line.

7. The semiconductor structure of claim 1 , wherein the MTJ comprises an MTJ layer between a top electrode and a bottom electrode of the MTJ, having a thickness of about 300 Å.

8. A semiconductor structure, comprising:
a magnetic random access memory (MRAM) cell, comprising:
a first N th metal line of an N th metal layer;
a magnetic tunneling junction (MTJ) over the first N th metal line; and
a first (N+M) th metal via of an (N+M) th metal layer, the first (N+M) th metal via being disposed over the MTJ layer,
wherein N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

9. The semiconductor structure of claim 8 , further comprising:
a logic periphery adjacent to the MRAM cell, comprising:
a second N th metal line of an N th metal layer;
a first N th metal via of the N th metal layer, the first N th metal via being disposed over the second N th metal line;
a first (N+M) th metal line of the (N+M) th metal layer, the first (N+M) th metal line being disposed over the first N th metal via; and
a second (N+M) th metal via of the (N+M) th metal layer, the second (N+M) th metal via being disposed over the first (N+M) th metal line.

10. The semiconductor structure of claim 8 , wherein a thickness measured from a bottom of the first N th metal via to a top of the first (N+M) th metal line is comparable to a thickness of the MTJ.

11. The semiconductor structure of claim 8 , wherein the MTJ comprises a top electrode electrically coupling to the first (N+M) th metal via.

12. The semiconductor structure of claim 8 , wherein the MTJ comprises a bottom electrode electrically coupling to the first N th metal line.

13. The semiconductor structure of claim 8 , wherein the first N th metal via and the first (N+M) th metal line in the logic periphery are surrounded by low-k dielectric.

14. The semiconductor structure of claim 8 , wherein the MTJ is surrounded by a nitride layer.

15. The semiconductor structure of claim 10 , wherein the first (N+M) th metal via and the second (N+M) th metal via are partially surrounded by SiC.

16. The semiconductor structure of claim 11 , wherein a top surface of the top electrode is substantially coplanar with a top surface of the first (N+M) th metal line.

17. A semiconductor structure, comprising:
a magnetic random access memory (MRAM) cell, comprising:
a first N th metal line of an N th metal layer;
a magnetic tunneling junction (MTJ) over the first N th metal line; and
a first (N+2) th metal via of an (N+2) th metal layer, the first (N+2) th metal via being disposed over the MTJ layer,
wherein N is an integer greater than or equal to 1.

18. The semiconductor structure of claim 17 , further comprising:
a logic periphery adjacent to the MRAM cell, comprising:
a second N th metal line of the N th metal layer; and
a second (N+2) th metal via of the (N+2) th metal layer, the second (N+2) th metal via being at the same level of the first (N+2) th metal via.

19. The semiconductor structure of claim 18 , wherein the logic periphery further comprising:
an N th metal via of the N th metal layer, the N th metal via being disposed on the second N th metal line; and
an (N+1) th metal line of an (N+1) th metal layer, the first (N+1) th metal line being disposed on the first N th metal via; and
an (N+1) th metal via of the (N+1) th metal layer, the (N+1) th metal via being disposed on the (N+1) th metal line.

20. The semiconductor structure of claim 19 , wherein the logic periphery further comprising:
an (N+2) th metal line of the (N+2) th metal layer, the (N+2) th metal line being disposed between the (N+1) th metal via and the second (N+2) th metal via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Harry-Hak-Lay
• Liao Chun-Heng

Classifications

• H01L43/08 Primary

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title