Magnetic memory devices

Patent metadata

Field	Value
Publication number	US-9634240-B2
Application number	US-201414567932-A
Country	US
Kind code	B2
Filing date	Dec 11, 2014
Priority date	Apr 4, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.

First claim

What is claimed is:

1. A magnetic memory device, comprising:
a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other;
a first insulating pattern between the plurality of first magnetic patterns to define the plurality of first magnetic patterns;
a tunnel barrier layer covering the plurality of first magnetic patterns and the first insulating pattern;
a plurality of bottom electrodes connected to the plurality of first magnetic patterns, respectively; and
a second insulating pattern between the plurality of bottom electrodes to define the plurality of bottom electrodes;
wherein the first insulating pattern includes a first magnetic element;
wherein the first magnetic element is the same as a second magnetic element constituting the plurality of first magnetic patterns;
wherein each of the plurality of bottom electrodes is spaced apart from the tunnel barrier layer with each of the plurality of first magnetic patterns interposed therebetween;
wherein the second insulating pattern includes a first element; and
wherein the first element is the same as a second element included in the plurality of bottom electrodes.

2. The magnetic memory device as set forth in claim 1 , wherein the first insulating pattern further includes oxygen.

3. The magnetic memory device as set forth in claim 1 , wherein electrical conductivity of the first insulating pattern is lower than electrical conductivity of the plurality of first magnetic patterns.

4. The magnetic memory device as set forth in claim 1 , wherein the first insulating pattern further includes impurities, the impurities being at least one selected from helium (He), phosphorus (P), arsenic (As), boron (B), and carbon (C).

5. The magnetic memory device as set forth in claim 1 , wherein the first insulating pattern is nonmagnetic.

6. The magnetic memory device as set forth in claim 1 ,
wherein a top surface of the first insulating pattern is substantially coplanar with a top surface of each of the plurality of first magnetic patterns, and
wherein a bottom surface of the first insulating pattern is substantially coplanar with a bottom surface of each of the plurality of first magnetic patterns.

7. The magnetic memory device as set forth in claim 1 ,
wherein the second insulating pattern includes a first metal element, and
wherein the first metal element is the same as a second metal element constituting the plurality of bottom electrodes.

8. The magnetic memory device as set forth in claim 7 , wherein the second insulating pattern further includes oxygen.

9. The magnetic memory device as set forth in claim 7 , wherein electrical conductivity of the second insulating pattern is lower than electrical conductivity of the plurality of bottom electrodes.

10. The magnetic memory device as set forth in claim 1 ,
wherein a top surface of the second insulating pattern is substantially coplanar with a top surface of each of the plurality of bottom electrodes, and
wherein a bottom surface of the second insulating pattern is substantially coplanar with a bottom surface of each of the plurality of bottom electrodes.

11. The magnetic memory device as set forth in claim 1 , wherein the first insulating pattern is in contact with the second insulating pattern.

12. The magnetic memory device as set forth in claim 1 , further comprising:
a plurality of second magnetic patterns on the substrate so as to be spaced apart from each other; and
a plurality of top electrodes connected to the plurality of second magnetic patterns, respectively,
wherein each of the plurality of second magnetic patterns is spaced apart from each of the plurality of first magnetic patterns with the tunnel barrier layer interposed therebetween and
wherein each of the plurality of second magnetic patterns overlaps each of the plurality of first magnetic patterns in a plan view.

13. The magnetic memory device as set forth in claim 1 , further comprising:
a top electrode layer on the tunnel barrier layer so as to cover the plurality of first magnetic patterns and the first insulating pattern; and
a second magnetic layer between the tunnel barrier layer and the top electrode layer so as to cover the plurality of first magnetic patterns and the first insulating pattern,
wherein the tunnel barrier layer is between the plurality of first magnetic patterns and the second magnetic layer.

14. The magnetic memory device as set forth in claim 1 ,
wherein the plurality of first magnetic patterns are between the substrate and the tunnel barrier layer, and
wherein each of the plurality of first magnetic patterns has a variable magnetization direction.

15. A magnetic memory device, comprising:
a plurality of first magnetic patterns on a substrate;
a plurality of first insulating patterns electrically isolating the plurality of first magnetic patterns from each other, wherein the plurality of first magnetic patterns and the plurality of first insulating patterns include a same magnetic element;
a tunnel barrier layer on the plurality of first magnetic patterns and the plurality of first insulating patterns;
a plurality of bottom electrodes contacting the plurality of first magnetic patterns;
a plurality of second insulating patterns electrically isolating the plurality of bottom electrodes from each other; and
a plurality of conductive pads electrically connecting the plurality of bottom electrodes, respectively, to the substrate;
wherein the plurality of bottom electrodes are separated from the plurality of conductive pads by a plurality of pillars so as to expose bottom surfaces of the plurality of second insulating patterns.

16. The magnetic memory device of claim 1 , wherein a first thickness of the tunnel barrier layer on the plurality of first insulating patterns is greater than a second thickness of the tunnel barrier layer on the plurality of first magnetic patterns.

17. The magnetic memory device of claim 15 , further comprising:
a plurality of pillar spacers conformally formed on sidewalls of the plurality of pillars,
wherein a thickness of each of the plurality of pillar spacers is equal to or greater than the sum of a height of each of the plurality of first magnetic patterns and a height of each of the plurality of bottom electrodes.

18. The magnetic memory device of claim 15 , further comprising:
a conductive layer electrically connected to the plurality of first magnetic patterns via either (i) a plurality of second magnetic patterns that correspond to the plurality of first magnetic patterns, or (ii) a magnetic layer covering the plurality of first insulating patterns and the plurality of first magnetic patterns.

Assignees

• Park Jongchul
• Bae Byoungjae
• Kang Shin-Jae
• Noh Eunsun
• Byun Kyung Rae
• Samsung Electronics Co Ltd

Inventors

• Park Jongchul
• Bae Byoungjae
• Kang Shin-Jae
• Noh Eunsun
• Byun Kyung Rae

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• H10N50/01

  Manufacture or treatment · CPC title

• H10N50/80 Primary

  Constructional details · CPC title