Wire bond free wafer level LED

Patent metadata

Field	Value
Publication number	US-9634191-B2
Application number	US-98541007-A
Country	US
Kind code	B2
Filing date	Nov 14, 2007
Priority date	Nov 14, 2007
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.

First claim

We claim:

1. A semiconductor device comprising:
an n-type epitaxial semiconductor layer comprising a first surface and a second surface opposite the first surface;
a p-type epitaxial semiconductor layer comprising a third surface and a fourth surface opposite the third surface;
an active region between the second surface and the fourth surface;
a wavelength conversion layer adjacent to at least a portion of the first surface of said n-type semiconductor layer, wherein the first surface is opposite the third surface of the p-type semiconductor layer;
a p-electrode comprising a lead that is accessible on the third surface, the third surface being opposite of a primary emission surface of said semiconductor device, said p-electrode electrically connected to said p-type layer;
an n-electrode comprising a lead that is accessible on the second surface, the second surface being opposite of said primary emission surface, said n-electrode electrically connected to said n-type layer; and
at least one spacer element, coupled to the n-electrode and the p-electrode, such that the at least one spacer element electrically isolates the n-electrode from the p-electrode, in which the n-electrode and the p-electrode extend laterally over the at least one spacer element,
wherein said first surface of said n-type epitaxial semiconductor layer is modified to enhance emission from said semiconductor device.

2. The semiconductor device of claim 1 , further comprising:
an n-pad contacting said n-type layer and providing an electrical connection between said n-type layer and said n-electrode; and
a p-pad contacting said p-type layer and providing an electrical connection between said p-type layer and said p-electrode.

3. The semiconductor device of claim 2 , wherein said n-pad partially overlaps said p-pad, said n- and p-pads electrically isolated by a spacer element.

4. The semiconductor device of claim 2 , wherein said p-pad partially overlaps said n-pad, said p- and n-pads electrically isolated by a spacer element.

5. The semiconductor device of claim 2 , wherein said p-pad comprises a reflective material.

6. The semiconductor device of claim 1 , said wavelength conversion layer comprising a phosphor layer opposite said leads of said n- and p-electrodes such that said phosphor layer comprises said primary emitting surface.

7. The semiconductor device of claim 6 , wherein said phosphor layer is disposed on said p-type layer.

8. The semiconductor device of claim 7 , further comprising a current spreading layer interposed between said phosphor layer and said p-type layer, said current spreading layer electrically connected to said p-electrode.

9. The semiconductor device of claim 1 , in which the at least one spacer element electrically isolates both said n- and p-electrodes from said active region.

10. The semiconductor device of claim 9 , wherein said at least one spacer element comprises a dielectric material.

11. The semiconductor device of claim 9 , wherein said at least one spacer element comprises a polymer.

12. The semiconductor device of claim 1 , wherein substantially all of said n-type layer, said active region and said p-type layer are above said p-electrode.

13. The semiconductor device of claim 1 , wherein said n-type layer, said p-type layer and said active region comprise materials from the Group-III Nitrides.

14. The semiconductor device of claim 1 , wherein the thickness of said p-electrode is at least 20 μm and the thickness of said n-electrode is at least 20 μm.

15. The semiconductor device of claim 1 , wherein the thickness of said p-electrode is at least 50 μm and the thickness of said n-electrode is at least 50 μm.

16. The semiconductor device of claim 1 , wherein substantially all of said n-type layer, said active region and said p-type layer are disposed between said n-electrode and said primary emission surface.

17. The semiconductor device of claim 1 , wherein said wavelength conversion layer is adjacent to said n-type semiconductor layer.

18. A semiconductor chip device, comprising:
an n-type semiconductor layer comprising a primary emission surface;
a p-type semiconductor layer;
an active region between said n- and p-type layers;
an n-electrode integral to said semiconductor chip device and comprising a lead that is accessible on a surface opposite said primary emission surface, said n-electrode electrically coupled to said n-type semiconductor layer;
a p-electrode integral to said semiconductor chip device and comprising a lead that is accessible on a surface opposite said primary emission surface, said p-electrode electrically coupled to said p-type semiconductor layer;
at least one spacer element, coupled to the n-electrode and the p-electrode, such that the at least one spacer element electrically isolates the n-electrode from the p-electrode and further electrically isolates the n-pad and the p-pad from the active region, in which the n-electrode and the p-electrode extend laterally over the at least one spacer element; and
a phosphor layer coupled to the primary emission surface, wherein said primary emission surface of said n-type semiconductor layer is modified.

19. The semiconductor device of claim 18 , further comprising:
an n-pad contacting said n-type layer and providing an electrical connection between said n-type layer and said n-electrode; and
a p-pad contacting said p-type layer and providing an electrical connection between said p-type layer and said p-electrode.

20. The semiconductor device of claim 19 , wherein said p-pad comprises a reflective material.

21. The semiconductor device of claim 18 , wherein the phosphor layer is coupled to the wafer opposite said leads of said n- and p-electrodes.

22. The semiconductor device of claim 18 , further comprising at least one spacer element configured to electrically isolate said n-electrode from said p-electrode and to electrically isolate both said n- and p-electrodes from said active region.

23. The semiconductor device of claim 18 , wherein substantially all of said n-type layer, said active region and said p-type layer are above said p-electrode.

24. The semiconductor device of claim 18 , wherein said n-type layer, said p-type layer and said active region comprise materials from the Group-III Nitrides.

25. The semiconductor device of claim 18 , wherein the thickness of said p-electrode is at least 50 μm and said n-electrode is at least 50 μm.

26. A semiconductor Group-III nitride device, comprising:
a flip-chip light emitting diode (LED) structure comprising an active region between a first surface of an n-type layer and a p-type layer;
an n-pad electrically coupled to the first surface of said n-type layer;
a wavelength conversion layer, coupled to at least a second surface of the n-type layer;
a p-pad electrically coupled to said p-type layer opposite an emission surface of the wavelength conversion layer, the emission surface of the wavelength conversion layer being opposite the second surface of the n-type layer;
at least one spacer element, coupled to at least the p-pad, in which the at least one spacer element electrically isolates the n-pad from the p-pad and further electrically isolates the n-pad and the p-pad from the active region; and
an electrode layer, coupled to the p-pad and the at least one spacer element, the electrode layer patterned into at least one n-electrode and at least one p-

Assignees

• Keller Bernd
• Chitnis Ashay
• Medendorp Jr Nicholas W
• Ibbetson James
• Batres Max
• Cree Inc

Inventors

• Keller Bernd
• Chitnis Ashay
• Medendorp Jr Nicholas W
• Ibbetson James
• Batres Max

Classifications

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H01L2224/49107

  Electricity · mapped topic