Method of manufacturing a device by locally heating one or more metalization layers and by means of selective etching

Patent metadata

Field	Value
Publication number	US-9634108-B2
Application number	US-201615017252-A
Country	US
Kind code	B2
Filing date	Feb 5, 2016
Priority date	Apr 23, 2007
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.

First claim

What is claimed is:

1. A device comprising:
a substrate; and
a metallization being locally arranged on a selected area of the substrate, the metallization comprising a metallization-layer compound, the metallization-layer compound being an alloy of at least two initial metals or an inter-metallic phase formed by different initial metals,
wherein the initial metals are such that the initial metals exhibit etching selectivities towards an etching medium, the etching selectivities being different than an etching selectivity of the alloy or the inter-metallic phase, and
wherein the metallization-layer compound is not provided on a further area of the substrate, the further area being adjacent to the selected area of the substrate.

2. The device as claimed in claim 1 , wherein the substrate is a semiconductor substrate having n- and p-doped areas, wherein a first metallization is locally arranged on the p-doped areas, the first metallization comprising a good ohmic contact behavior toward the semiconductor substrate, wherein a second metallic layer is formed over an entire area of the first metallization and the n-doped areas, the second metallic layer forming, with the n-doped areas, a blocking Schottky contact, and wherein a further metallic layer is configured such that it fully or partly covers the second metallic layer and serves to improve the contact.

3. The device as claimed in claim 1 , wherein the substrate is a semiconductor substrate comprising a trough having a first doping characteristic, which differs, in terms of its doping characteristic, from a second doping characteristic with which a semiconductor region surrounding the trough is doped, the device comprising a gate region within the trough, which is doped with the second doping characteristic, and comprising a metallization which has a source contact and a separate drain contact within the trough, and a separate gate contact within the gate region.

4. The device as claimed in claim 3 , wherein an overall layer thickness of the metallization ranges between 10 nm and 20 μm.

5. The device as claimed in claim 1 , wherein the metallization comprises a surface having a surface roughness less than a boundary roughness, the boundary roughness being less than or equal to a roughness which may be achieved by means of an etching process.

6. The device as claimed in claim 5 , wherein the surface roughness is less than 0.5 nm rms.

7. A cascode circuit comprising a device comprising:
a substrate; and
a metallization being locally arranged on a selected area of the substrate, the metallization comprising a metallization-layer compound, the metallization-layer compound being an alloy of at least two initial metals or an inter-metallic phase formed by different initial metals,
wherein the initial metals are such that the initial metals exhibit etching selectivities towards an etching medium, the etching selectivities being different than an etching selectivity of the alloy or the inter-metallic phase, and
wherein the metallization-layer compound is not provided on a further area of the substrate, the further area being adjacent to the selected area of the substrate.

8. The cascode circuit as claimed in claim 7 , wherein the substrate is a semiconductor substrate having n- and p-doped areas, wherein a first metallization is locally arranged on the p-doped areas, the first metallization comprising a good ohmic contact behavior toward the semiconductor substrate, wherein a second metallic layer is formed over an entire area of the first metallization and the n-doped areas, the second metallic layer forming, with the n-doped areas, a blocking Schottky contact, and wherein a further metallic layer is configured such that it fully or partly covers the second metallic layer and serves to improve the contact.

9. The cascode circuit as claimed in claim 7 , wherein the substrate is a semiconductor substrate comprising a trough having a first doping characteristic, which differs, in terms of its doping characteristic, from a second doping characteristic with which a semiconductor region surrounding the trough is doped, the device comprising a gate region within the trough, which is doped with the second doping characteristic, and comprising a metallization which has a source contact and a separate drain contact within the trough, and a separate gate contact within the gate region.

10. The cascode circuit as claimed in claim 9 , wherein an overall layer thickness of the metallization ranges between 10 nm and 20 μm.

11. The cascode circuit as claimed in claim 7 , wherein the metallization comprises a surface having a surface roughness less than a boundary roughness, the boundary roughness being less than or equal to a roughness which may be achieved by means of an etching process.

12. The cascode circuit as claimed in claim 11 , wherein the surface roughness is less than 0.5 nm rms.

Assignees

• Infineon Technologies Ag

Inventors

• Rupp Roland
• Woehlert Stefan
• Gutt Thomas
• Treu Michael

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H10D64/0123

  to silicon carbide · CPC title

• H10D64/0115 Primary

  to silicon carbide · CPC title

• H10W20/43

  Layouts of interconnections · CPC title