Vertical memory devices

Patent metadata

Field	Value
Publication number	US-9634023-B2
Application number	US-201514605529-A
Country	US
Kind code	B2
Filing date	Jan 26, 2015
Priority date	Feb 3, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance layer, a plurality of vertical channels on the channel layer, and a plurality of gate lines. The vertical channels extend in a first direction that is perpendicular with respect to a top surface of the channel layer. The gate lines surround outer sidewalls of the vertical channels, and are stacked in the first direction and are spaced apart from each other.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a lower substrate;
a peripheral circuit on the lower substrate;
a lower insulation layer on the lower substrate, the lower insulation layer covering the peripheral circuit;
an upper substrate on the lower substrate, the upper substrate covering the lower insulation layer, the upper substrate including a low resistance layer and a channel layer sequentially formed on the lower substrate, the low resistance layer including a metallic material;
a plurality of vertical channels directly on the channel layer and on the low resistance layer, the vertical channels extending in a first direction that is perpendicular with respect to a top surface of the channel layer, the vertical channels including outer sidewalls, the vertical channels being over the low resistance layer in the first direction; and
a plurality of gate lines surrounding the outer sidewalls of the vertical channels, the gate lines being stacked in the first direction and spaced apart from each other.

2. The vertical memory device of claim 1 , further comprising:
an ohmic contact layer between the low resistance layer and the channel layer.

3. The vertical memory device of claim 2 , wherein
the ohmic contact layer and the channel layer include polysilicon doped with p-type impurities, and
an impurity concentration of the ohmic contact layer is greater than an impurity concentration of the channel layer.

4. The vertical memory device of claim 1 , wherein
the lower insulation layer is interposed between the lower substrate and the upper substrate.

5. The vertical memory device of claim 4 , further comprising:
an ohmic contact pattern on the low resistance layer, wherein
the lower insulation layer includes at least one trench,
the low resistance layer fills a lower portion of the trench, and
the ohmic contact pattern fills a remaining portion of the trench.

6. The vertical memory device of claim 1 , wherein the low resistance layer includes at least one of a metal, a metal nitride and a metal silicide, and
an electrical resistance of the low resistance layer is less than an electrical resistance of the channel layer.

7. A vertical memory device, comprising:
a lower substrate;
a peripheral circuit on the lower substrate;
a lower insulation layer on the lower substrate, the lower insulation layer covering the peripheral circuit;
an upper substrate on the lower substrate, the upper substrate including a first channel layer and a second channel layer which are spaced apart from each other in a first direction that is perpendicular with respect to a top surface of the first channel layer;
a plurality of vertical channels on the first channel layer, the vertical channels extending in the first direction; and
a plurality of gate lines, the gate lines surrounding outer sidewalls of the vertical channels, the gate lines being stacked in the first direction and spaced apart from each other in the first direction on the second channel layer.

8. The vertical memory device of claim 7 , further comprising:
a semiconductor pattern connecting the first channel layer and the second channel layer to each other,
wherein the vertical channels are on the semiconductor pattern.

9. The vertical memory device of claim 8 , wherein
the second channel layer surrounds an outer sidewall of the semiconductor pattern, and
the second channel layer is configured to serve as a channel of a ground selection transistor (GST).

10. The vertical memory device of claim 7 , wherein
the vertical channel includes a first vertical channel and a second vertical channel,
wherein the first vertical channel is on the second channel layer, and
the second vertical channel is adjacent to an inner wall of the first vertical channel and extends through the second channel layer.

11. The vertical memory device of claim 10 , wherein the second vertical channel is in contact with the first channel layer.

12. The vertical memory device of claim 7 , wherein
the first channel layer and the second channel layer include polysilicon doped with p-type impurities, and
an impurity concentration of the first channel layer is greater than an impurity concentration of the second channel layer.

13. The vertical memory device of claim 7 , wherein the upper substrate further includes an insulation layer interposed between the first channel layer and the second channel layer.

14. The vertical memory device of claim 7 , wherein
the first channel layer includes a plurality of line patterns, and
each one of the line patterns overlaps at least one channel row including the plurality of the vertical channels.

15. The vertical memory device of claim 7 , wherein the upper substrate covers the lower insulation layer.

16. A vertical memory device, comprising:
a lower substrate;
a peripheral circuit on the lower substrate;
a lower insulation layer on the lower substrate, the lower insulation layer covering the peripheral circuit;
a plurality of gate lines on the lower insulation layer, the gate lines spaced apart from each other in a first direction, the gate lines defining channel holes and openings;
a channel layer between the gate lines and the lower insulation layer;
a plurality of vertical channels on the lower insulation layer, the vertical channels extending in the first direction through the channel holes of the gate lines; and
at least one of a low resistance layer and a well layer between the lower insulation layer and the vertical channels in the first direction.

17. The vertical memory device of claim 16 , wherein
the low resistance layer is between the lower insulation layer and the vertical channels,
the channel layer is between the vertical channels and the low resistance layer, and
a resistance of the channel layer is greater than a resistance of the low resistance layer.

18. The vertical memory device of claim 16 , further comprising:
a semiconductor pattern on the lower insulation layer, wherein
the vertical channels are on the semiconductor pattern.

19. The vertical memory device of claim 16 , further comprising:
an insulation layer, wherein
the well layer is between the lower insulation layer and the vertical channels,
the channel layer is on the insulation layer, and
the insulation layer is between the well layer and the channel layer.

20. The vertical memory device of claim 16 , further comprising:
bit lines electrically connected to the vertical channels;
a common source line; and
a dielectric layer structure in the channel holes, wherein
the dielectric layer structure is between the vertical channels and the gate lines,
the channel layer includes impurity regions exposed by the openings in the gate lines, and
the common source line is electrically connected to the impurity regions.

Assignees

• Lee Chang-Hyun
• Samsung Electronics Co Ltd

Inventors

• Lee Chang-Hyun

Classifications

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H01L29/16

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic