BICMOS device having commonly defined gate shield in an ED-CMOS transistor and base in a bipolar transistor

Patent metadata

Field	Value
Publication number	US-9633994-B2
Application number	US-201615050684-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	May 23, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate;
a bipolar transistor region developed above the substrate;
a metal oxide semiconductor (MOS) transistor region developed above the substrate and spaced apart from the bipolar transistor region;
a base defined from a single polysilicon layer and by a single mask to position above the bipolar transistor region; and
a gate shield defined from the single polysilicon layer and by the single mask to position above the MOS transistor region.

2. The integrated circuit of claim 1 , wherein the MOS transistor region includes a laterally diffused metal oxide semiconductor (LDMOS) transistor region.

3. The integrated circuit of claim 1 , wherein the MOS transistor region includes an extended drain metal oxide semiconductor (EDMOS) transistor region.

4. The integrated circuit of claim 1 , wherein the MOS transistor region includes a vertical drain metal oxide semiconductor (VDMOS) transistor region.

5. The integrated circuit of claim 1 , wherein the single polysilicon layer includes an epitaxial polysilicon layer.

6. The integrated circuit of claim 1 , further comprising:
a buried layer on the substrate,
wherein the bipolar transistor region is positioned above the buried layer, and
wherein the MOS transistor region is positioned above the buried layer.

7. The integrated circuit of claim 1 , further comprising:
a body region positioned within the MOS transistor region;
a drain well positioned within the MOS transistor region and spaced apart from the body region; and
a gate structure positioned above the body region, and the gate structure free of overlapping the drain well,
wherein the gate shield is positioned laterally above the gate structure and extends to partially overlap the drain well.

8. The integrated circuit of claim 7 , further comprising:
a drain region positioned within the drain well;
a gate electrode coupled to the gate structure; and
a drain electrode coupled to the drain region,
wherein the gate shield is positioned between the gate electrode and the drain electrode.

9. The integrated circuit of claim 7 , further comprising:
a drain region positioned within the drain well;
a source region positioned within the body region;
a source electrode coupled to the source region; and
a drain electrode coupled to the drain region,
wherein the gate shield is positioned between the source electrode and the drain electrode.

10. The integrated circuit of claim 7 , wherein the gate structure is insulated from the gate shield.

11. The integrated circuit of claim 1 , further comprising:
a body region positioned within the MOS transistor region;
a drain well positioned within the MOS transistor region and spaced apart from the body region;
a shallow trench isolation (STI) structure positioned within the MOS transistor region and between the drain well and the body region; and
a gate structure positioned above the body region, and the gate structure free of overlapping the drain well and the STI structure,
wherein the gate shield is positioned laterally above the gate structure and extends to partially overlap with the STI structure.

12. The integrated circuit of claim 1 , further comprising:
a gate shield electrode coupled to the gate shield and configured to receive a shield bias voltage.

13. The integrated circuit of claim 1 , wherein the single polysilicon layer includes a P doped silicide material.

14. The integrated circuit of claim 1 , further comprising:
a first deep trench isolation channel laterally surrounding the bipolar transistor region; and
a second deep trench isolation channel laterally surrounding the MOS transistor region.

15. An integrated circuit, comprising:
a substrate;
a bipolar transistor region developed above the substrate;
a laterally diffused metal oxide semiconductor (LDMOS) transistor region developed above the substrate and spaced apart from the bipolar transistor region;
a base defined from a single polysilicon layer and by a single mask to position above the bipolar transistor region; and
a gate shield defined from the single polysilicon layer and by the single mask to position above the LDMOS transistor region.

16. The integrated circuit of claim 15 , further comprising:
a body region positioned within the LDMOS transistor region;
a drain well positioned within the LDMOS transistor region and spaced apart from the body region; and
a gate structure positioned above the body region, and the gate structure free of overlapping the drain well,
wherein the gate shield is positioned laterally above the gate structure and extends to partially overlap with the drain well.

17. The integrated circuit of claim 16 , further comprising:
a drain region positioned within the drain well;
a gate electrode coupled to the gate structure; and
a drain electrode coupled to the drain region,
wherein the gate shield is positioned between the gate electrode and the drain electrode.

18. An integrated circuit, comprising:
a substrate;
a bipolar transistor region developed above the substrate;
an extended drain metal oxide semiconductor (EDMOS) transistor region developed above the substrate and spaced apart from the bipolar transistor region;
a base defined from a single polysilicon layer and by a single mask to position above the bipolar transistor region; and
a gate shield defined from the single polysilicon layer and by the single mask to position above the EDMOS transistor region.

19. The integrated circuit of claim 18 , further comprising:
a body region positioned within the EDMOS transistor region;
a drain well positioned within the EDMOS transistor region and spaced apart from the body region;
a shallow trench isolation (STI) structure positioned within the EDMOS transistor region and between the drain well and the body region; and
a gate structure positioned above the body region, and the gate structure free of overlapping the drain well and the STI structure, and
wherein the gate shield is positioned laterally above the gate structure and extends to partially overlap with the STI structure.

20. The integrated circuit of claim 19 , further comprising:
a drain region positioned within the drain well;
a gate electrode coupled to the gate structure; and
a drain electrode coupled to the drain region,

wherein the gate shield positioned between the gate electrode and the drain electrode.

Assignees

• Texas Instruments Inc

Inventors

• Babcock Jeffrey A
• Sadovnikov Alexei

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H01L29/66712

  Electricity · mapped topic

• H01L29/423

  Electricity · mapped topic

• H01L29/7816

  Electricity · mapped topic

• H01L29/66689

  Electricity · mapped topic