Bi-directional ESD protection device

Patent metadata

Field	Value
Publication number	US-9633990-B2
Application number	US-201615188235-A
Country	US
Kind code	B2
Filing date	Jun 21, 2016
Priority date	Dec 29, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.

First claim

What is claimed is:

1. A process of forming a standalone bidirectional bipolar ESD transistor comprising the steps:
providing a substrate wafer of a first doping type;
forming a well photo resist pattern on the substrate;
implanting well dopant of a second doping type to form a well;
forming a shallow trench isolation (STI) pattern on the substrate;
etching a STI trench over the boundary between the well and the substrate and etching a STI trench over a base of the bidirectional bipolar ESD transistor;
forming dielectric STI geometries in the shallow trenches wherein a first STI geometry separates an emitter region from the boundary and wherein a second STI geometry separates a collector region from the boundary; and
implanting dopant of the first dopant type into the emitter region to form an emitter diffusion and into the collector region to form a collector diffusion wherein the emitter diffusion and the collector diffusion are identical.

2. The process of claim 1 further comprising the steps:
forming a first diode active area between the emitter region and the boundary of the well;
forming a second diode active area between the collector region and the boundary of the well;
implanting dopant of the first dopant type into the first diode active area to form a first base biasing diode;
implanting dopant of the first dopant type into the second diode active area to form a second base biasing diode;
coupling the first base biasing diode between the base and the emitter diffusion; and
coupling the second base biasing diode between the base and the collector diffusion.

3. The process of claim 2 further including:
forming a deep diode pattern on the substrate with a first opening over first diode active area and with a second opening over the second diode active area;
implanting dopant of the first dopant type to form a first deep diode and to form a second deep diode wherein the first deep diode is disposed below and coupled to the first diode and wherein the second deep diode is disposed below and coupled to the second diode.

4. The process of claim 1 , wherein the first doping type is n-type, the second doping type is p-type and the standalone bidirectional bipolar ESD transistor is a bidirectional NPN bipolar transistor.

5. A process of forming a bidirectional ESD device comprising:
forming a well photo resist pattern on a substrate of a first doping type;
implanting well dopant of a second doping type to form a well;
forming a shallow trench isolation (STI) pattern on the substrate;
etching a STI trench over a lateral boundary between the well and the substrate and etching a STI trench over a base of the bidirectional ESD device;
forming dielectric STI geometries in the STI trenches wherein a first STI geometry separates an emitter region from the boundary and wherein a second STI geometry separates a collector region from the boundary; and
simultaneously implanting dopant of the first dopant type into the emitter region to form an emitter diffusion and into the collector region to form a collector diffusion.

6. The process of claim 5 , further comprising the steps:
forming a first diode active area between the emitter region and the lateral boundary of the well;
forming a second diode active area between the collector region and the lateral boundary of the well;
implanting dopant of the first dopant type into the first diode active area to form a first base biasing diode;
implanting dopant of the first dopant type into the second diode active area to form a second base biasing diode;
coupling the first base biasing diode between the base and the emitter diffusion; and
coupling the second base biasing diode between the base and the collector diffusion.

7. The process of claim 6 , further including:
forming a deep diode pattern on the substrate with a first opening over first diode active area and with a second opening over the second diode active area;
implanting dopant of the first dopant type to form a first deep diode and to form a second deep diode wherein the first deep diode is disposed below and coupled to the first diode and wherein the second deep diode is disposed below and coupled to the second diode.

8. The process of claim 5 , wherein the first doping type is n-type, the second doping type is p-type and the bidirectional ESD device is a bidirectional NPN bipolar transistor.

Assignees

• Texas Instruments Inc

Inventors

• Salman Akram A
• Farbiz Farzan
• Appaswamy Aravind C
• Concannon Ann Margaret

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H01L21/8222

  Electricity · mapped topic

• H01L27/0259 Primary

  Electricity · mapped topic

• H01L29/6625

  Electricity · mapped topic