Semiconductor fin structures and methods for forming the same

Patent metadata

Field	Value
Publication number	US-9633905-B2
Application number	US-201213452516-A
Country	US
Kind code	B2
Filing date	Apr 20, 2012
Priority date	Apr 20, 2012
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.

First claim

What is claimed is:

1. A device comprising:
a semiconductor substrate;
a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate;
a Shallow Trench Isolation (STI) region on a side of the plurality of semiconductor fins, wherein the STI region comprises a top surface and a non-flat bottom surface, and wherein the plurality of semiconductor fins is over the top surface of the STI region;
a plurality of STI regions in the semiconductor substrate;
a plurality of fin extensions underlying and aligned to the plurality of semiconductor fins, wherein sidewalls of the plurality of fin extensions are in contact with sidewalls of the plurality of STI regions; and
a fin extension residue having a bottom substantially level with bottom surfaces of the plurality of fin extensions, wherein the fin extension residue extends into the STI region from a bottom surface of the STI region.

2. The device of claim 1 , wherein the plurality of fin extensions has a first pitch, and wherein the fin extension residue and a nearest one of the plurality of semiconductor fins have a second pitch substantially equal to the first pitch.

3. The device of claim 1 , wherein the fin extension residue has a width substantially equal to a width of one of the plurality of fin extensions.

4. A device comprising:
a semiconductor substrate;
a plurality of Shallow Trench Isolation (STI) regions in the semiconductor substrate;
a plurality of semiconductor fins parallel to each other and in the semiconductor substrate;
a plurality of fin extensions underlying and aligned to the plurality of semiconductor fins, wherein the plurality of STI regions is disposed between the plurality of fin extensions;
an edge STI region on a side of the plurality of fin extensions, wherein the edge STI region comprises a first bottom surface substantially level with bottom surfaces of the plurality of STI regions, and a second bottom surface higher than the first bottom surface; and
a fin extension residue having a bottom substantially level with bottoms of the plurality of fin extensions, wherein the fin extension residue extends into the edge STI region, and wherein a top surface of the fin extension residue is in contact with the second bottom surface of the edge STI region.

5. The device of claim 4 , wherein the first bottom surface of the edge STI region comprises portions on opposite sides of the second bottom surface of the edge STI region.

6. The device of claim 4 , wherein the edge STI region comprises portions encircling the fin extension residue.

7. The device of claim 4 further comprising:
a gate dielectric on sidewalls and top surfaces of the plurality of semiconductor fins; and
a gate electrode over the gate dielectric, wherein the gate electrode overlaps the edge STI region.

8. The device of claim 4 , wherein the fin extension residue and a nearest one of the plurality of fin extensions have a pitch substantially equal to a pitch of the plurality of semiconductor fins.

9. The device of claim 4 , wherein the fin extension residue has a width substantially equal to a width of one of the plurality of fin extensions.

Assignees

• Chen Ryan Chia-Jen
• Lin Yih-Ann
• Lin Chia Tai
• Chen Chao-Cheng
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Ryan Chia-Jen
• Lin Yih-Ann
• Lin Chia Tai
• Chen Chao-Cheng

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/76232

  Electricity · mapped topic

• H01L29/6681

  Electricity · mapped topic