Integrated circuit package with active interposer

Patent metadata

Field	Value
Publication number	US-9633872-B2
Application number	US-201313752808-A
Country	US
Kind code	B2
Filing date	Jan 29, 2013
Priority date	Jan 29, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal.

First claim

What is claimed is:

1. An integrated circuit package comprising:
a substrate;
an interposer having a plurality of embedded switching elements disposed over the substrate, wherein the plurality of embedded switching elements receives a plurality of power supply signals; and
an integrated circuit having a plurality of circuit blocks disposed over the substrate, wherein the plurality of embedded switching elements provides at least one circuit block of the plurality of circuit blocks with a selected power supply signal of the plurality of power supply signals.

2. The integrated circuit package defined in claim 1 , wherein each circuit block of the plurality of circuit blocks includes a control circuit that controls at least one embedded switching element from the plurality of embedded switching elements.

3. The integrated circuit package defined in claim 2 , wherein the plurality of embedded switching elements comprises a plurality of transistors each having a source-drain terminal that receives a power supply signal of the plurality of power supply signals, and wherein each control circuit controls a respective set of embedded switching elements of the plurality of embedded switching elements.

4. The integrated circuit package defined in claim 3 , wherein the control circuit provides a control signal to a gate of at least one transistor of the plurality of transistors and wherein the control circuit activates the transistor using the control signal.

5. The integrated circuit package defined in claim 3 wherein the plurality of transistors comprises a plurality of P-type metal-oxide-field-effect-transistors.

6. The integrated circuit package defined in claim 1 , wherein the interposer comprises a substrate layer and a plurality of redistribution layers, wherein the plurality of redistribution layers comprises a plurality of interconnects that is coupled to the integrated circuit, wherein the plurality of embedded switching elements is formed in the substrate layer, and wherein the plurality of embedded switching elements is coupled to the integrated circuit through the plurality of interconnects.

7. The integrated circuit package defined in claim 1 further comprising:
an additional integrated circuit disposed over the interposer, wherein the plurality of switching elements in the interposer transmits a plurality of power supply signals to the integrated circuit and the additional integrated circuit.

8. An integrated circuit device comprising:
an integrated circuit having a plurality of logic regions, wherein a first portion of the plurality of logic regions receives a first power supply signal and wherein a second portion of the plurality of logic regions receives a second power supply signal; and
an interposer having a plurality of switching elements coupled to the integrated circuit, wherein, in a first configuration, a first switching element provides the first portion of the plurality of logic regions with the first power supply signal, and wherein a second switching element provides the second portion of the plurality of logic regions with the second power supply signal.

9. The integrated circuit device defined in claim 8 , wherein the first and second power supply signals comprise first and second voltage levels, respectively, wherein, in a second configuration, the first switching element provides the second portion of the plurality of logic regions with the first power supply signal and the second switching element provides the first portion of the plurality of logic regions with the second power supply signal.

10. The integrated circuit device defined in claim 8 , wherein each switching element of the plurality of switching elements is selected from the group consisting of: a P-type metal-oxide-field-effect-transistor, an N-type metal-oxide-field-effect-transistor, and a Micro-Electro-Mechanical switches.

11. The integrated circuit device defined in claim 8 further comprising:
first control circuitry in the first portion of the plurality of logic regions; and
second control circuitry in the second portion of the plurality of logic regions, wherein the first and second control circuitries selectively enable the first and second switching elements, respectively.

12. The integrated circuit device defined in claim 11 , wherein the first and second control circuitries receive a control signal selected from the group consisting of: a configuration random access memory bit, a user input, an output signal from external circuitry, and a predetermined voltage level.

13. The integrated circuit device defined in claim 8 further comprising:
an additional integrated circuit coupled to the interposer layer, wherein the additional integrated circuit comprises an additional plurality of logic regions, wherein the plurality of switching elements provides the additional plurality of logic regions with a plurality of power supply signals.

14. The integrated circuit device defined in claim 8 , wherein the interposer comprises a substrate layer and a plurality of redistribution layers, wherein the plurality of redistribution layers includes a plurality of interconnects that is coupled to the integrated circuit, and wherein the plurality of switching elements is formed in the substrate layer.

15. The integrated circuit device defined in claim 14 , wherein the substrate layer includes a plurality of through-silicon vias and wherein the plurality of switching elements is coupled to the integrated circuit through the plurality of interconnects in the plurality of redistribution layers.

16. A method of packaging an integrated circuit, the method comprising:
forming a plurality of switching elements in an interposer;
mounting the interposer on a package substrate; and
mounting an integrated circuit having a plurality of logic regions on the interposer, wherein each switching element of the plurality of switching elements provides the plurality of logic regions with a selected power supply signal through a plurality of interconnects.

17. The method defined in claim 16 , wherein the interposer includes a substrate layer and a plurality of redistribution layers, and wherein forming the plurality of switching elements comprises:
depositing a silicon oxide layer over a dielectric layer on the substrate layer;
depositing a polysilicon layer over the silicon oxide layer;
removing a portion of the polysilicon layer and the silicon oxide layer to form at least one gate stack;
implanting a source region and a drain region in the substrate layer; and
forming a plurality of contacts over the source and drain regions and the at least one gate stack.

18. The method defined in claim 17 further comprising:
implanting an n-well region in the substrate, wherein implanting the source and drain regions in the substrate layer comprises implanting the source and drain regions in the n-well region.

19. The method defined in claim 16 further comprising:
mounting an additional integrated circuit having an additional plurality of logic regions on the interposer wherein each switching element of the plurality of switching elements provides the additional plurality of logic regions with an additional selected power supply signal through the plurality of interconnects.

20. The method defined in claim 16 further comprising:
forming a diode in the interposer prior to the disposing of the interposer over the package substrate.

21. The method defined in claim 16 further comprising:
forming a de-coupling capacitor in the i

Assignees

• Altera Corp

Inventors

• Chen Shuxian
• Watt Jeffrey T

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title