Internal plasma grid applications for semiconductor fabrication

Patent metadata

Field	Value
Publication number	US-9633846-B2
Application number	US-201514954586-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Apr 5, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

First claim

What is claimed is:

1. A method of reflowing photoresist, the method comprising:
receiving a substrate in a reaction chamber, the substrate having photoresist patterned thereon, wherein the reaction chamber comprises a grid structure dividing the interior of the reaction chamber into an upper sub-chamber proximate a plasma generator and a lower sub-chamber proximate a substrate holder;
flowing a first plasma generating gas into the upper sub-chamber;
generating a first plasma in the upper sub-chamber from the first plasma generating gas, the first plasma having a first electron density, and generating a second plasma in the lower sub-chamber, wherein the second plasma is an ion-ion plasma that has a second electron density at least about 10 times lower than the first electron density;
exposing the substrate to the second plasma to smooth the photoresist;
flowing a second plasma generating gas into the upper sub-chamber;
generating a third plasma in the upper sub-chamber from the second plasma generating gas, the third plasma having a third electron density, and generating a fourth plasma in the lower sub-chamber, wherein the fourth plasma is an ion-ion plasma that has a fourth electron density at least about 10 times lower than the third electron density; and
exposing the substrate to the fourth plasma,
wherein before exposing the substrate to the second plasma the photoresist has an initial line width roughness, wherein after exposing the substrate to the fourth plasma the photoresist has a final line width roughness, and wherein the final line width roughness is about 75% or less of the initial line width roughness.

2. The method of claim 1 ,
wherein exposing the substrate to the fourth plasma removes photoresist in a foot region of the photoresist.

3. The method of claim 1 , wherein the first plasma generating gas comprises at least one gas selected from the group consisting of: H 2 , Ar, HBr, and combinations thereof.

4. The method of claim 3 , wherein the first plasma generating gas further comprises N 2 and/or HeSTG.

5. The method of claim 3 , wherein the first plasma generating gas comprises H 2 .

6. The method of claim 1 , wherein the second plasma generating gas comprises at least one gas selected from the group consisting of Ar, HBr, and a combination thereof.

7. The method of claim 6 , wherein the second plasma generating gas comprises Ar.

8. The method of claim 7 , wherein the first plasma generating gas comprises H 2 .

9. The method of claim 1 , wherein exposing the substrate to the second plasma both (i) smooths the photoresist, and (ii) removes the photoresist in a foot region of the photoresist.

10. The method of claim 9 , wherein the first plasma generating gas comprises H 2 , N 2 , and HeSTG.

11. The method of claim 1 , wherein the photoresist comprises extreme ultraviolet photoresist.

12. The method of claim 1 , further comprising applying a bias voltage to the substrate while the substrate is exposed to the fourth plasma, wherein the bias voltage is about 200V or less.

13. The method of claim 12 , wherein the bias voltage is greater than about 30V.

14. The method of claim 1 , wherein before exposing the substrate to the second plasma the photoresist has an initial height, wherein after exposing the substrate to the fourth plasma the photoresist has a final height, and wherein the final height is at least about 50% of the initial height.

15. The method of claim 1 , wherein the final line width roughness is about 65% or less of the initial line width roughness.

16. The method of claim 1 , wherein the first plasma has a first electron temperature of about 2 eV or more, and wherein the second plasma has a second effective electron temperature of about 1 eV or less.

17. The method of claim 1 , wherein the second electron density is about 5×10 9 cm −3 or less.

18. The method of claim 1 , wherein a ratio of negative ions:positive ions in the second plasma is between about 0.5-1.

19. The method of claim 1 , wherein the first plasma is an inductively coupled plasma generated at a power between about 300-1000 Watts per substrate.

20. The method of claim 19 , wherein a bias applied to the substrate is between about 50-200 V.

21. The method of claim 1 , wherein after smoothing the photoresist, the substrate has a line width roughness of about 3.0 nm or below.

22. The method of claim 1 ,
wherein the first plasma generating gas and the second plasma generating gas have different compositions.

23. The method of claim 22 , wherein the first plasma generating gas comprises H 2 , and wherein the second plasma generating gas does not comprise H 2 .

Assignees

• Lam Res Corp

Inventors

• Paterson Alex
• Kim Do Young
• Kamarthy Gowri
• Del Puppo Helene
• Yu Jen-Kan
• Titus Monica
• Mani Radhika
• Sun Noel Yui
• Gani Nicolas
• Kimura Yoshie
• Chung Ting-Ying

Classifications

• H10P50/287

  by chemical means · CPC title

• H10P50/268

  of silicon-containing layers · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title