Readiness signaling between master and slave controllers of a liquid crystal display

Patent metadata

Field	Value
Publication number	US-9633611-B2
Application number	US-201214117902-A
Country	US
Kind code	B2
Filing date	May 17, 2012
Priority date	May 18, 2011
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A liquid crystal display includes a liquid crystal panel and a first to nth control substrates (n is an integer which is 2 or greater) which control the liquid crystal panel. When the first control substrate enters an operable status, the first control substrate transmits a readiness signal to the second control substrate which is at a next stage, and when the nth control substrate determines that the nth control substrate receives a readiness signal from a control substrate at a previous stage and is in an operable status, the nth control substrate transmits a readiness signal to the first control substrate, thereby being able to suppress a synchronization failure between the plurality of control substrates which are provided in a liquid crystal display.

First claim

The invention claimed is:

1. A liquid crystal display comprising:
a liquid crystal panel having n separate display areas wherein n is an integer which is 2 or greater; and
first to nth control substrates which control the respective display areas,
wherein, when a power supply voltage of the first control substrate becomes equal to or larger than a first threshold, the first control substrate transmits a readiness signal to the second control substrate which is at a next stage,
wherein, the nth control substrate transmits a readiness signal to the first control substrate based on the nth control substrate receiving a readiness signal from a control substrate at a previous stage and a power supply voltage of the nth control substrate becoming equal to or larger than an nth threshold,
wherein the first control substrate receives a readiness signal from the nth control substrate and transmits a reset release signal to all of other control substrates,
wherein reset states of the other control substrates are released in response to the reset release signal,
wherein a timing controller is provided on each of the first to nth control substrates and the respective timing controllers are operated in synchronization with each other based on a synchronization signal, and
wherein preparations of operations of timing controllers provided on the other control substrates are completed by the reset release signal.

2. The liquid crystal display according to claim 1 ,
wherein the liquid crystal panel contains a first to nth areas in which displays are controlled by the first to nth control substrates, respectively.

3. The liquid crystal display according to claim 1 ,
wherein, after the first control substrate transmits the reset release signal, the first control substrate transmits the synchronization signal to all of other control substrates.

4. The liquid crystal display according to claim 1 ,
wherein a power supply circuit is provided on each of the first to nth control substrates.

5. The liquid crystal display according to claim 4 ,
wherein the control substrates other than the first control substrate are provided with synchronization circuits generating a readiness signal for its own stage based on a readiness signal from a control substrate at a previous stage and a supply voltage from a power supply circuit.

6. The liquid crystal display according to claim 1 ,
wherein the readiness signal is a differential signal.

7. The liquid crystal display according to claim 1 ,
wherein the synchronization signal is a differential signal.

8. The liquid crystal display according to claim 1 ,
wherein the reset release signal is a differential signal.

9. The liquid crystal display according to claim 1 ,
wherein:
two gate drivers driving a same scan signal line are provided;
one of the first to nth control substrates controls one of the two gate drivers; and
another of the first to nth control substrates controls another of the two gate drivers.

Assignees

• Inoue Akihiko
• Sharp Kk

Inventors

• Inoue Akihiko

Classifications

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title

• G09G3/3655

  Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G3/3666

  with the matrix divided into sections · CPC title

• G09G3/3659

  the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes · CPC title