Method, system, and computer program product for verifying an electronic design using stall prevention requirements of electronic circuit design models of the electronic design

Patent metadata

Field	Value
Publication number	US-9633153-B1
Application number	US-201414588287-A
Country	US
Kind code	B1
Filing date	Dec 31, 2014
Priority date	Dec 31, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Various mechanisms and approaches identify multiple cells in an electronic design and multiple sets of stall prevention requirements or multiple sets of transactions for the multiple cells and determine dependencies between stall prevention requirements. A graph is constructed to represent the dependencies and the stall prevention requirements or the transactions involved in the dependencies by using the stall prevention requirements or the transactions as the nodes and the dependencies as the arcs connecting the nodes in the graph. One or more loop analyses are performed on the graph to identify one or more loops as one or more potential deadlocks. False deadlocks may be eliminated from further processing. The analyses and deadlock detection may be independently performed for each cell in sequence or in parallel to divide and conquer a complex electronic system design.

First claim

We claim:

1. A computer implemented method for verifying an electronic design using stall prevention requirements of electronic design circuit models of the electronic design, comprising:
configuring at least a stall prevention requirement generation module function in tandem with at least one microprocessor to perform a process, the process comprising:
identifying one or more blocks of circuit component designs of an electronic design and one or more sets of stall prevention requirements corresponding to the one or more blocks;
determining dependencies between stall prevention requirements;
generating a graph for the dependencies at least by correlating the stall prevention requirements with one another; and
verifying the electronic design with at least a false deadlock module that analyzes one or more loops identified from the graph to detect at least one false deadlock in one or more potential deadlocks identified from the one or more loops.

2. The computer implemented method of claim 1 , wherein the electronic design model comprises a register transfer level (RTL) electronic design, and the one or more blocks of circuit component designs are interconnected in a switch fabric at a system level of the register transfer level electronic design.

3. The computer implemented method of claim 1 , further comprising:
identifying one or more forward progress requirements for interconnects connecting the one or more blocks in the electronic design; and
identifying one or more environment stall conditions by proving or disproving the one or more environment stall conditions with the at least one processor.

4. The computer implemented method of claim 3 , further comprising:
identifying a first block from the one or more blocks; and
identifying a first transaction for data transport involving the first block with the at least one processor that identifies a first specification of data in the data transport entering or exiting the first block.

5. The computer implemented method of claim 4 , further comprising:
identifying one or more other transactions for one or more other blocks with the at least one processor that identifies a specification of the data in the data transport entering or exiting the one or more other blocks; and
determining dependencies between the first transaction for the data transport involving the first block and the one or more other transactions for the data transport involving the one or more other blocks in the electronic design.

6. The computer implemented method of claim 3 , further comprising:
identifying a first block from the one or more blocks; and
identifying a stall prevention requirement for the first block with the at least one processor that transforms an environment stall condition of the one or more environment stall conditions into the stall prevention requirement.

7. The computer implemented method of claim 6 , identifying the stall prevention requirement for the first block comprising:
identifying a stall state involving the first block with the at least one processor that processes the environment stall condition to retrieve the stall state associated with or in the environment stall condition;
identifying an unblocking event corresponding to the stall state with the at least one processor that processes the environment stall condition to retrieve the unblocking event associated with or in the environment stall condition;
transforming information about the stall state into a precondition of the stall prevention requirement; and
transforming information about the unblocking event into an implication of the stall prevention requirement.

8. The computer implemented method of claim 6 , in which determining the dependencies is performed sequentially for the one or more blocks in the electronic design, the one or more blocks includes at least one cell that has been proven to perform the data transport across or in the at least one cell is deadlock free, and the data transport that is deadlock free across or in the at least one cell does not ensure that the data transport in or out of the at least one cell in the electronic design is deadlock free.

9. The computer implemented method of claim 6 , further comprising:
identifying one or more other stall prevention requirements for one or more other blocks with the at least one processor that transforms one or more other environment stall conditions of the one or more environment stall conditions for the one or more other blocks into the one or more stall prevention requirements.

10. The computer implemented method of claim 9 , further comprising:
determining dependencies between the stall prevention requirement for the first block and the one or more other stall prevention requirements for the one or more other blocks in the electronic design.

11. The computer implemented method of claim 10 , determining the graph further comprising:
determining a plurality of nodes in the graph with the at least one processor that identifies and transforms the stall prevention requirement and the one or more other stall prevention requirements into the plurality of nodes; and
determining a plurality of arcs connecting the plurality of nodes in the graph with the at least one processor that identifies and transforms the dependencies into the plurality of nodes.

12. The computer implemented method of claim 1 , further comprising:
detecting one or more potential deadlocks in the electronic design with the at least one processor that performs one or more loop analyses on the graph and identifies the one or more potential deadlocks based in part or in whole upon results of the one or more loop analyses.

13. The computer implemented method of claim 12 , further comprising:
identifying zero or more false deadlocks in the electronic design with the at least one processor that examines the one or more potential deadlocks to identify the zero or more false deadlocks; and
trimming a processing space to a smaller processing space with the at least one processor that eliminates the zero or more false deadlocks from further processing and reports one or more remaining potential deadlock for debugging, analysis, or fixing.

14. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor, causes the at least one processor to perform a process for verifying an electronic design using stall prevention requirements of electronic design circuit models of the electronic design, the process comprising:
identifying one or more blocks of circuit component designs of an electronic design and one or more sets of stall prevention requirements corresponding to the one or more blocks by using at least one processor;
determining dependencies between stall prevention requirements with the at least one processor;
generating a graph for the dependencies at least by correlating the stall prevention requirements with one another; and
verifying the electronic design with at least a false deadlock module that analyzes one or more loops identified from the graph to detect at least one false deadlock in one or more potential deadlocks identified from the one or more loops.

15. The article of manufacture of claim 14 , further comprising the sequence of instructions which, when executed by at least one processor, causes the at least one processor to perform the process that further comprises:
identifying a first block from the one or more blocks; and
identifying a stall prevention requirement for the first block with the at least one pro

Assignees

• Cadence Design Systems Inc

Inventors

• Khaikin Sergey
• Loh Lawrence Chunkhang

Classifications

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F17/5045 Primary

  Physics · mapped topic