Implementing an inter-processor communication in a multi-core system using mmWave radios

Patent metadata

Field	Value
Publication number	US-9632968-B2
Application number	US-201113993212-A
Country	US
Kind code	B2
Filing date	Dec 15, 2011
Priority date	Dec 15, 2011
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A system and method are provided that implement the use of mmWave directional communications to replace wired interconnects for inter-processor communication in multi-core computing systems. Using highly directional, low interference mmWave transmissions in the 60 GHz frequency range, an alternative interconnect scheme is provided to support inter-processor communication in multi-core computing systems for operations and testing. Wired interconnects between the multiple cores and a bus interface are replaced with cooperating mmWave transmitting/receiving devices on each of the core side and the bus interface side. The ability to transmit and receive separate high data rate, directional low interference signals for individual core communication is thus facilitated between the bus interface and each of the multiple cores in the multi-core computing system.

First claim

We claim:

1. A method for implementing inter-processor communication, comprising:
pairing a first plurality directional wireless transmitters/receivers individually connected to a plurality of CPU cores with a cooperating second plurality of directional wireless transmitters/receivers individually connected to a plurality of ports in a bus interface: and
implementing, with a processor, an inter-processor communication scheme between the plurality of CPU cores via a plurality of individual wireless communication links established between cooperating pairs of the first plurality of CPU core-connected directional wireless transmitters/receivers and the second plurality of interface port-connected directional wireless transmitters/receivers;
wherein inter-processor communication is selectively done through mmWave radios operating at a same frequency or at a different frequency;
wherein the plurality of individual wireless communication links supporting data transmission rates greater than 6 Gbps;
wherein sub-carrier frequencies for the plurality of individual wireless communication links being individually selectable.

2. The method of claim 1 , the respective the first plurality of CPU core-connected directional wireless transmitters/receivers and the second plurality of interface port-connected directional wireless transmitters/receivers being mmWave transmitters/receivers.

3. The method of claim 2 , the mmWave transmitters/receivers operating in the 60 GHz frequency range.

4. The method of claim 1 , the first plurality directional wireless transmitters/receivers being individually connected to the plurality of CPU cores via individual wired connections.

5. The method of claim 1 , the second plurality directional wireless transmitters/receivers being individually connected to the plurality of ports in the bus interface via individual wired connections.

6. The method of claim 1 , the inter-processor communication scheme being implemented in an operating multi-core computing system.

7. The method of claim 1 , the inter-processor communication scheme be implemented for testing of a multi-core computing system.

8. The method of claim 1 , further comprising monitoring characteristics of the plurality of individual wireless communication links.

9. A system for implementing inter-processor communication, comprising:
a first plurality directional wireless transmitters/receivers individually connected to a plurality of CPU cores:
a second plurality of directional wireless transmitters/receivers individually connected to a plurality of ports in a bus interface: and
a processor that is programmed to implement an inter-processor communication scheme between the plurality of CPU cores via a plurality of individual wireless communication links established between cooperating pairs of the first plurality of CPU core-connected directional wireless transmitters/receivers and the second plurality of interface port-connected directional wireless transmitters/receivers;
wherein inter-processor communication is selectively done through mmWave radios operating at a same frequency or at a different frequency;
wherein the plurality of individual wireless communication links supporting data transmission rates greater than 6 Gbps;
wherein sub-carrier frequencies for the plurality of individual wireless communication links being individually selectable for the cooperating pairs of the CPU core-connected directional wireless transmitters/receivers and the interface port-connected directional wireless transmitters/receivers.

10. The system of claim 9 , the first plurality of directional wireless transmitters/receivers and the second plurality of directional wireless transmitters/receivers being mmWave transmitters/receivers.

11. The system of claim 10 , the mmWave transmitters/receivers operating in the 60 GHz frequency range.

12. The system of claim 9 , the first plurality directional wireless transmitters/receivers being individually connected to the plurality of CPU cores via individual wired connections.

13. The system of claim 9 , the second plurality directional wireless transmitters/receivers being individually connected to the plurality of ports in the bus interface via individual wired connections.

14. The system of claim 9 , the processor implementing the inter-processor communication scheme in an operating multi-core computing system in which the first plurality directional wireless transmitters/receivers, the plurality of CPU cores, the second plurality of directional wireless transmitters/receivers, the bus interface and the processor are installed.

15. The system of claim 9 , the processor implementing the inter-processor communication scheme to test a multi-core computing system in a test apparatus, the test apparatus including the first plurality directional wireless transmitters/receivers, the plurality of CPU cores, the second plurality of directional wireless transmitters/receivers, the bus interface and the processor.

16. A non-transitory computer-readable medium storing computer-readable instructions which, when executed by a processor, cause the processor to execute a method for implementing inter-processor communication, comprising:
pairing a first plurality directional wireless transmitters/receivers individually connected to a plurality of CPU cores with a cooperating second plurality of directional wireless transmitters/receivers individually connected to a plurality of ports in a bus interface: and
implementing an inter-processor communication scheme between the plurality of CPU cores via a plurality of individual wireless communication links established between cooperating pairs of the first plurality of CPU core-connected directional wireless transmitters/receivers and the second plurality of interface port-connected directional wireless transmitters/receivers;
wherein inter-processor communication is selectively done through mmWave radios operating at a same frequency or at a different frequency;
wherein the plurality of individual wireless communication links supporting data transmission rates greater than 6 Gbps;
wherein sub-carrier frequencies for the plurality of individual wireless communication links being individually selectable for the cooperating pairs of the CPU core-connected directional wireless transmitters/receivers and the interface port-connected directional wireless transmitters/receivers.

Assignees

• Cordeiro Carlos
• Li Guoqing
• Sadeghi Bahareh
• Intel Corp

Inventors

• Cordeiro Carlos
• Li Guoqing
• Sadeghi Bahareh

Classifications

• G06F15/167

  using a common memory, e.g. mailbox · CPC title

• G06F13/42 Primary

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F15/163

  Interprocessor communication · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title