Providing input/output virtualization (IOV) by mapping transfer requests to shared transfer requests lists by IOV host controllers

Patent metadata

Field	Value
Publication number	US-9632953-B2
Application number	US-201514728343-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Jun 3, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.

First claim

What is claimed is:

1. An input/output virtualization (IOV) host controller (HC) (IOV-HC) communicatively coupled to a plurality of input/output (I/O) clients via a corresponding plurality of client register interfaces (CRIs), and to a flash-memory-based storage device;
the IOV-HC comprising:
a plurality of transfer request list (TRL) slot offset registers, each indicating a slot of a shared TRL that is assigned as a base slot to each CRI of the plurality of CRIs; and
a plurality of TRL slot count registers, each indicating a number of slots of the shared TRL assigned to each CRI of the plurality of CRIs; and

the IOV-HC configured to:
receive a transfer request (TR) directed to the flash-memory-based storage device from a CRI of the plurality of CRIs; and
map, by a TR fetch circuit of the IOV-HC, the TR to a slot of the shared TRL based on a TRL slot offset register of the plurality of TRL slot offset registers and a TRL slot count register of the plurality of TRL slot count registers, the TRL slot offset register and the TRL slot count register corresponding to the CRI.

2. The IOV-HC of claim 1 , configured to map the TR to the slot of the shared TRL based on a sum of a slot identifier of the TR and a TRL slot offset register value of the TRL slot offset register.

3. The IOV-HC of claim 1 , further configured to:
receive, from the flash-memory-based storage device, a response to the TR; and
route, by the IOV-HC, the response to the CRI based on the TRL slot offset register and the TRL slot count register corresponding to the CRI.

4. The IOV-HC of claim 1 , further configured to receive, from a virtual machine manager (VMM), a TRL slot offset register value and a TRL slot count register value for each CRI of the plurality of CRIs, responsive to initialization of the IOV-HC.

5. The IOV-HC of claim 1 , further configured to receive, from a VMM, a TRL slot offset register value and a TRL slot count register value for a new CRI corresponding to a new I/O client, responsive to creation of the new I/O client by the VMM.

6. The IOV-HC of claim 1 , further comprising:
a plurality of task management request list (TMRL) slot offset registers, each indicating a slot of a shared TMRL that is assigned as a base slot to each CRI of the plurality of CRIs;
a plurality of TMRL slot count registers, each indicating a number of slots of the shared TMRL assigned to each CRI of the plurality of CRIs; and
the IOV-HC further configured to:
receive a task management request (TMR) from a CRI of the plurality of CRIs; and
map, by the TR fetch circuit of the IOV-HC, the TMR to a slot of the shared TMRL based on a TMRL slot offset register of the plurality of TMRL slot offset registers and a TMRL slot count register of the plurality of TMRL slot count registers, the TMRL slot offset register and the TMRL slot count register corresponding to the CRI.

7. The IOV-HC of claim 1 , communicatively coupled to the flash-memory-based storage device according to an Embedded MultiMedia Card (eMMC) standard.

8. The IOV-HC of claim 1 , communicatively coupled to the flash-memory-based storage device according to a Universal Flash Storage (UFS) standard.

9. The IOV-HC of claim 1 integrated into an integrated circuit (IC).

10. The IOV-HC of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

11. A method for providing virtual transfer request lists (TRLs) for multiple hosts, comprising:
receiving, by an input/output virtualization (IOV) host controller (HC) (IOV-HC), a transfer request (TR) directed to a flash-memory-based storage device from a client register interface (CRI) of a plurality of CRIs; and
mapping, by a TR fetch circuit of the IOV-HC, the TR to a slot of a shared TRL based on a TRL slot offset register of a plurality of TRL slot offset registers and a TRL slot count register of a plurality of TRL slot count registers, the TRL slot offset register and the TRL slot count register corresponding to the CRI;
wherein:
the plurality of TRL slot offset registers each indicates a slot of the shared TRL that is assigned as a base slot to a corresponding CRI of the plurality of CRIs; and
the plurality of TRL slot count registers each indicates a number of slots of the shared TRL assigned to the corresponding CRI of the plurality of CRIs.

12. The method of claim 11 , wherein mapping the TR to the slot of the shared TRL is based on a sum of a slot identifier of the TR and a TRL slot offset register value of the TRL slot offset register.

13. The method of claim 11 , further comprising:
receiving, from the flash-memory-based storage device, a response to the TR; and
routing the response to the CRI based on the TRL slot offset register and the TRL slot count register corresponding to the CRI.

14. The method of claim 11 , further comprising receiving, from a virtual machine manager (VMM), a TRL slot offset register value and a TRL slot count register value for each CRI of the plurality of CRIs, responsive to initialization of the IOV-HC.

15. The method of claim 11 , further comprising receiving, from a VMM, a TRL slot offset register value and a TRL slot count register value for a new CRI corresponding to a new input/output (I/O) client, responsive to creation of the new I/O client by the VMM.

16. The method of claim 11 , further comprising:
receiving, by the IOV-HC, a task management request (TMR) from a CRI of the plurality of CRIs; and
mapping, by the TR fetch circuit of the IOV-HC, the TMR to a slot of a shared task management request list (TMRL) based on a TMRL slot offset register of a plurality of TMRL slot offset registers and a TMRL slot count register of a plurality of TMRL slot count registers, the TMRL slot offset register and the TMRL slot count register corresponding to the CRI;
wherein:
the plurality of TMRL slot offset registers each indicates a slot of the shared TMRL that is assigned as a base slot to the corresponding CRI of the plurality of CRIs; and
the plurality of TMRL slot count registers each indicates a number of slots of the shared TMRL assigned to the corresponding CRI of the plurality of CRIs.

17. The method of claim 11 , wherein the flash-memory-based storage device comprises an Embedded MultiMedia Card (eMMC) device.

18. The method of claim 11 , wherein the flash-memory-based storage device comprises a Universal Flash Storage (UFS) device.

19. An input/output virtualization (IOV) host controller (HC) (IOV-HC), comprising:
a means for receiving a transfer request (TR) directed to a flash-memory-based storage device from a client register interface (CRI) of a plurality of CRIs; and
a means for mapping the TR to a slot of a shared transfer request list (TRL) based on a TRL slot offset register of a plurality of TRL slot offset registers and a TRL slot count register of a plurality of TRL slot count registers, the TRL slot offset register and the TRL slot count register corresponding to the CRI;
wherein:
the plurality of TRL slot offset registers each indicates a slot of the shared TR

Assignees

• Qualcomm Inc

Inventors

• Shacham Assaf
• Raviv Dolev
• Teb David

Classifications

• G06F3/0664

  at device level, e.g. emulation of a storage device or system · CPC title

• G06F3/06

  Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers} · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title