Translating an address associated with a command communicated between a system and memory circuits

Patent metadata

Field	Value
Publication number	US-9632929-B2
Application number	US-67292407-A
Country	US
Kind code	B2
Filing date	Feb 8, 2007
Priority date	Feb 9, 2006
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

First claim

What is claimed is:

1. An apparatus comprising:
an interface circuit electrically connected to a first number of physical dynamic random access memory (“DRAM”) devices via multiple data paths including a first data path and a distinct second data path, wherein each of the physical DRAM devices is an individual and independent monolithic device, the interface circuit configured to:
communicate with the first number of physical DRAM devices and a memory controller,
interface the first number of physical DRAM devices to simulate a different, second number of virtual DRAM devices, such that the first number of physical DRAM devices appear to the memory controller as the second number of virtual DRAM devices, each of the virtual DRAM devices being simulated as an individual and independent monolithic device,
simulate a first virtual DRAM device using a first physical DRAM device on the first data path and a second physical DRAM device on the distinct second data path,
use both a physical row of the first physical DRAM device and a physical row of the second physical DRAM device to simulate a virtual row of the first virtual DRAM device,
receive a row-access command from the memory controller, directed to the first virtual DRAM device, for the virtual row of the first virtual DRAM device,
receive a column-access command from the memory controller, directed to the first virtual DRAM device, for a particular column of the virtual row, wherein the column-access command from the memory controller is received before the row-access command is used to activate any physical DRAM device,
based on the received column-access command, translate the row-access command for the virtual row to a row-access command for either the physical row of the first physical DRAM device or the physical row of the second physical DRAM device that corresponds to part of the virtual row, and
activate either the physical row of the first physical DRAM device or the physical row of the second physical DRAM device based on the translated row-access command to activate only part of the virtual row.

2. The apparatus of claim 1 , wherein the first number of physical DRAM devices are associated with first command scheduling constraints and the different, second number of virtual DRAM devices are associated with second command scheduling constraints different from the first command scheduling constraints; and
the interface circuit is further configured to interface the first number of physical DRAM devices to the memory controller such that the first command scheduling constraints are met.

3. The apparatus of claim 2 , wherein the first command scheduling constraints and the second command scheduling constraints include intra-device command scheduling constraints.

4. The apparatus of claim 3 , wherein the intra-device command scheduling constraints include at least one of a column-to-column delay time (tCCD), a row-to-row activation delay time (tRRD), a four-bank activation window time (tFAW), or a write-to-read turn-around time (tWTR).

5. The apparatus of claim 2 , wherein the first command scheduling constraints and the second command scheduling constraints include inter-device command scheduling constraints.

6. The apparatus of claim 5 , wherein the inter-device command scheduling constraints include at least one of a rank-to-rank data bus turnaround time or an on-die-termination (ODT) control switching time.

7. The apparatus of claim 1 , wherein the interface circuit includes a circuit that is positioned on a dual-inline memory module (DIMM).

8. The apparatus of claim 1 , wherein the interface circuit is a circuit separate from the physical DRAM devices and is positioned on a dual-inline memory module (DIMM) with the physical DRAM devices.

9. A method, comprising:
interfacing a first number of physical dynamic random access memory (“DRAM”) devices via multiple data paths including a first data path and a distinct second data path to simulate a different, second number of virtual DRAM devices, such that the first number of physical DRAM devices appear to the memory controller as the second number of virtual DRAM devices, wherein each of the physical DRAM devices and the virtual DRAM devices is an individual and independent monolithic device;
simulating a first virtual DRAM device using a first physical DRAM device on the first data path and a second physical DRAM device on the distinct second data path;
using both a physical row of the first physical DRAM device and a physical row of the second physical DRAM device to simulate a virtual row of the first virtual DRAM device;
receiving a row-access command from the memory controller, directed to the first virtual DRAM device, for the virtual row of the first virtual DRAM device;
receiving a column-access command from the memory controller, directed to the first virtual DRAM device, for a particular column of the virtual row, wherein the column access command from the memory controller is received before the row-access command is used to activate any physical DRAM device;
based on the received column-access command, translating the row-access command for the virtual row to a row-access command for either the physical row of the first physical DRAM device or the physical row of the second physical DRAM device that corresponds to part of the virtual row; and
activating either the physical row of the first physical DRAM device or the physical row of the second physical DRAM device based on the translated row-access command to activate only part of the virtual row.

10. The method of claim 9 , wherein the first number of physical DRAM devices is associated with first command scheduling constraints and the different, second number of virtual DRAM devices is associated with second command scheduling constraints different from the first command scheduling constraints; and
wherein the first command scheduling constraints and the second command scheduling constraints include intra-device command scheduling constraints.

11. The method of claim 10 , wherein the intra-device command scheduling constraints include at least one of a column-to-column delay time (tCCD), a row-to-row activation delay time (tRRD), a four-bank activation window time (tFAW), or a write-to-read turn-around time (tWTR).

12. The method of claim 9 , wherein the first number of physical DRAM devices is associated with first command scheduling constraints and the different, second number of virtual DRAM devices is associated with second command scheduling constraints different from the first command scheduling constraints; and
wherein the first command scheduling constraints and the second command scheduling constraints include inter-device command scheduling constraints.

13. The method of claim 12 , wherein the inter-device command scheduling constraints include at least one of a rank-to-rank data bus turnaround time or an on-die-termination (ODT) control switching time.

14. A system, comprising:
a first number of physical dynamic random access memory (“DRAM”) devices; and
an interface circuit electrically connected to the first number of physical DRAM devices via multiple data paths including a first data path and a distinct second data path, wherein each of the physical DRAM devices is an individual and independent monolithic device, the interface circuit configured to:
communicate with the first number of physical DRAM devices and a memory controller,
interface the first number of physical DRAM devices to simulate a different, second number of virtual DRAM devices, such that the first number of physical DRAM devices appear to the memory controller as th

Assignees

• Rajan Suresh Natarajan
• Schakel Keith R
• Smith Michael John Sebastian
• Wang David T
• Weber Frederick Daniel
• Google Inc

Inventors

• Rajan Suresh Natarajan
• Schakel Keith R
• Smith Michael John Sebastian
• Wang David T
• Weber Frederick Daniel

Classifications

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F12/0292 Primary

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G06F13/4243

  with synchronous protocol · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title