Faster reconstruction of segments using a dedicated spare memory unit

Patent metadata

Field	Value
Publication number	US-9632891-B2
Application number	US-201514620650-A
Country	US
Kind code	B2
Filing date	Feb 12, 2015
Priority date	Feb 12, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Techniques for faster reconstruction of segments using a dedicated spare memory unit are described. Zone segments in memory units are associated with a dedicated spare memory unit. The zone segments are reconstructed in the dedicated spare memory unit in response to a failed memory unit except for an identified failed zone segment of the failed memory unit. The identified failed zone segment of the failed memory unit is retained in the dedicated spare unit. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. A method, comprising:
segmenting a first memory unit, a second memory unit, and a third memory unit of a memory unit group into a plurality of zone segments;
associating the plurality of zone segments with a dedicated spare memory unit assigned to the memory unit group;
retaining, in the dedicated spare memory unit, a first failed zone segment of the first memory unit having failed and a second failed zone segment of the second memory unit having failed;
reconstructing, in the dedicated spare memory unit, a third zone segment of the third memory unit;
promoting the dedicated spare memory unit as a first replacement memory unit for the first memory unit;
assigning a spare memory unit as a second replacement memory unit for the second memory unit; and
copying the second failed zone segment of the second memory unit from the first replacement memory unit to the second replacement memory unit.

2. The method of claim 1 , comprising:
reconstructing, in the second replacement memory unit, remaining zone segments in response to the first memory unit and the second memory unit failing.

3. The method of claim 1 , comprising:
responsive to a prediction that the first memory unit will fail:
promoting the dedicated spare memory unit as the first replacement memory unit for the first memory unit;
retaining zone segments, in the first replacement memory unit, that relate to zone segments within the first memory unit predicted to fail; and
copying remaining zone segments in the first memory unit to the first replacement memory unit.

4. The method of claim 1 , wherein the retaining comprises:
utilizing a logical block address segment lock to retain the first failed zone segment and the second failed zone segment.

5. The method of claim 1 , wherein the assigning a spare memory unit comprises:
promoting the spare memory unit from a pool of global spare memory units.

6. The method of claim 1 , comprising:
responsive to the first replacement memory unit replacing the first memory unit and the second replacement memory unit replacing the second memory unit:
reassigning a second spare memory unit from a pool of global spare memory units as a new dedicated spare memory unit;
segmenting the first replacement memory unit, the second replacement memory unit, and the third memory unit into a new plurality of zone segments; and
associating the new plurality of zone segments with the new dedicated spare memory unit.

7. The method of claim 1 , comprising performing a mirror copy into the dedicated spare memory unit for a write operation into one of the plurality of zone segments.

8. The method of claim 1 , comprising:
specifying that a total number of the plurality of zone segments is to equal a total number of memory units in the memory unit group, the total number of memory units in the memory unit group comprising one or more parity memory units assigned to the memory unit group; and
specifying that a size of each of the plurality of zone segments is to equal a size of a memory unit divided by the total number of memory units in the memory unit group.

9. A computing device, comprising:
a memory having stored thereon instructions for performing a method; and
a processor coupled to the memory, the processor configured to execute the instructions to cause the processor to:
segment a first memory unit, a second memory unit, and a third memory unit of a memory unit group into a plurality of zone segments;
associate the plurality of zone segments with a dedicated spare memory unit;
retain, in the dedicated spare memory unit, a first failed zone segment of the first memory unit having failed and a second failed zone segment of the second memory unit having failed;
reconstruct, in the dedicated spare memory unit, a third zone segment of the third memory unit;
promote the dedicated spare memory unit as a first replacement memory unit for the first memory unit;
assign a spare memory unit as a second replacement memory unit for the second memory unit; and
copy the second failed zone segment of the second memory unit from the first replacement memory unit to the second replacement memory unit.

10. The computing device of claim 9 , wherein the instructions cause the processor to:
reconstruct, in the second replacement memory unit, remaining zone segments.

11. The computing device of claim 9 , wherein the instructions cause the processor to:
responsive to the first replacement memory unit replacing the first memory unit and the second replacement memory unit replacing the second memory unit:
reassign a second spare memory unit from a pool of global spare memory units as a new dedicated spare memory unit;
segment the first replacement memory unit, the second replacement memory unit, and the third memory unit into a new plurality of zone segments; and
associate the new plurality of zone segments with the new dedicated spare memory unit.

12. The computing device of claim 9 , wherein the instructions cause the processor to:
copy the plurality of zone segments into the dedicated spare memory unit when the dedicated spare memory unit is first assigned to the memory unit group.

13. The computing device of claim 9 , wherein the instructions cause the processor to:
perform a mirror copy into the dedicated spare memory unit.

14. The computing device of claim 9 , wherein the instructions cause the processor to:
specify that a total number of the plurality of zone segments is to equal a total number of memory units in the memory unit group, the total number of memory units in the memory unit group comprising one or more parity memory units assigned to the memory unit group.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed, cause a processor to:
segment a first memory unit, a second memory unit, and a third memory unit of a memory unit group into a plurality of zone segments;
associate the plurality of zone segments with a dedicated spare memory unit;
retain, in the dedicated spare memory unit, a first failed zone segment of the first memory unit having failed and a second failed zone segment of the second memory unit having failed;
reconstruct, in the dedicated spare memory unit, a third zone segment of the third memory unit;
promote the dedicated spare memory unit as a first replacement memory unit for the first memory unit;
assign a spare memory unit as a second replacement memory unit for the second memory unit; and
copy the second failed zone segment of the second memory unit from the first replacement memory unit to the second replacement memory unit.

16. The computer-readable storage medium of claim 15 , comprising further instructions that, when executed, cause the processor to:
responsive to the first replacement memory unit replacing the first memory unit and the second replacement memory unit replacing the second memory unit:
reassign a second spare memory unit from a pool of global spare memory units as a new dedicated spare memory unit;
segment the first replacement memory unit, the second replacement memory unit, and the third memory unit into a new plurality of zone segments; and associate the new plurality of zone segments with the new dedicated spare memory unit.

17. The computer-readable storage medium of claim 15 , comprising further instructions that, when executed, cause the processor to:
promote the spare memory unit from a pool of global spare memory units.

18. The computer-readable storage medium of claim 15 , comprising furt

Assignees

• Netapp Inc

Inventors

• Thomas Arvind
• Bysani Premnath

Classifications

• G06F11/1666

  where the redundant component is memory or memory area · CPC title

• G06F11/1088

  Reconstruction on already foreseen single or plurality of spare disks · CPC title

• G06F3/065

  Replication mechanisms · CPC title

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F3/0647

  Migration mechanisms · CPC title