Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-9632856-B2
Application number	US-201614992472-A
Country	US
Kind code	B2
Filing date	Jan 11, 2016
Priority date	Feb 26, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

First claim

What is claimed is:

1. A memory device comprising:
an error detector configured to detect a number of error bits in data read from a memory cell in response to a received first command; and
a correction status information generator configured to output correction status information associated with the read data, the correction status information indicating whether the detected number of error bits is greater than or equal to a first threshold value;
wherein the memory device is configured to
receive a second command from a memory controller, and
perform a memory operation in response to the second command and prior to output of corrected data to the memory controller; and

wherein the corrected data is associated with the read data.

2. The memory device of claim 1 , wherein the correction status information generator is further configured to output the correction status information to the memory controller.

3. The memory device of claim 1 , further comprising:
an error correction circuit configured to correct errors in the read data; and
a data output circuit configured to output the corrected data.

4. The memory device of claim 3 , wherein the data output circuit is further configured to output the corrected data without receiving an additional command from the memory controller.

5. The memory device of claim 3 , wherein the data output circuit is further configured to output the corrected data in response to a third command.

6. The memory device of claim 5 , wherein the third command is a read command or a buffer read command.

7. The memory device of claim 3 , wherein the data output circuit is configured to output the corrected data after a first delay period.

8. The memory device of claim 7 , wherein the first delay period is a correction latency.

9. The memory device of claim 7 , wherein the memory device is configured to ignore additional commands from the memory controller during the first delay period.

10. The memory device of claim 1 , further comprising:
a first terminal configured to transmit or receive data to or from the memory controller; and
a second terminal configured to receive a data masking signal from the memory controller; wherein
the correction status information generator is further configured to output the correction status information through any one of the first and second terminals.

11. The memory device of claim 1 , further comprising:
a first terminal not related to reception of data or a data masking signal; wherein
the correction status information generator is further configured to output the correction status information through the first terminal.

12. The memory device of claim 1 , wherein the correction status information generator is further configured to output first information indicating whether an uncorrectable error is generated in the read data.

13. The memory device of claim 12 , further comprising:
a first terminal configured to transmit or receive data to or from the memory controller; and
a second terminal configured to receive a data masking signal from the memory controller;
wherein the correction status information generator is further configured to
output the correction status information through one of the first and second terminals, and
output the first information through another one of the first and second terminals.

14. The memory device of claim 12 , further comprising:
a first terminal configured to receive a data masking signal or data from the memory controller; and
a second terminal not related to reception of the data masking signal or the data from the memory controller;
wherein the correction status information generator is further configured to
output the correction status information through one of the first and second terminals, and
output the first information through another one of the first and second terminals.

15. A memory device comprising:
a cell array including a plurality of memory cells;
an error detector configured to perform error detection with respect to data read from the plurality of memory cells in response to a first command; and
an information generator configured to output first information indicating whether the read data is valid or not, according to a result of the performed error detection;
wherein, when the read data is not valid, the memory device is configured to output the first information to a memory controller without outputting corrected data associated with the read data to the memory controller.

16. The memory device of claim 15 , wherein the information generator is further configured to output the first information indicating that the read data is not valid when an error generated in the read data is correctable.

17. The memory device of claim 15 , wherein the information generator is further configured to output the first information indicating that the read data is valid when no error is generated in the read data.

18. The memory device of claim 15 , wherein
the information generator is further configured to output the first information indicating that the read data is valid when no error is generated in the read data or only one error bit is generated in the read data; and
the information generator is further configured to output the first information indicating that the read data is not valid when at least two error bits are generated in the read data.

19. The memory device of claim 15 , wherein the information generator is further configured to output second information indicating whether an uncorrectable error is generated in the read data.

20. The memory device of claim 15 , further comprising:
an error corrector configured to perform an error correction with respect to invalid data; and
a storage unit configured to store error-corrected data corrected by the error corrector, and to output the error-corrected data in response to a second command.

21. The memory device of claim 20 , wherein the memory device is configured to receive at least one third command and perform a memory operation in response to the received at least one third command, before the error-corrected data is output.

Assignees

• Chung Hoi-Ju
• Kim Su-A
• Seo Mu-Jin
• Yu Hak-Soo
• Youn Jae-Youn
• Choi Hyo-Jin
• Samsung Electronics Co Ltd

Inventors

• Chung Hoi-Ju
• Kim Su-A
• Seo Mu-Jin
• Yu Hak-Soo
• Youn Jae-Youn
• Choi Hyo-Jin

Classifications

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/076 Primary

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title