Non-preemption of a group of interchangeable tasks in a computing device

Patent metadata

Field	Value
Publication number	US-9632845-B2
Application number	US-201414471814-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Dec 12, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A method for non-preemption of interchangeable tasks is disclosed. The method for non-preemption of interchangeable tasks includes identifying a first task assigned to a first time slice, identifying a second task assigned to a subsequent time slice, comparing the first task to the second task, identifying whether the first task and the second task are interchangeable tasks, and executing the first task during the subsequent time slice in response to the first task and the second task being interchangeable. The first task may be currently executing on a processor or may be scheduled to execute on the processor.

First claim

What is claimed is:

1. A method comprising:
identifying a first task that is one of executing and scheduled to execute on a processor during a first time slice;
identifying a second task scheduled to be executed on the processor during a subsequent time slice immediately adjacent to the first time slice, the first time slice occurring before the subsequent time slice;
comparing the first task to the second task;
identifying whether the first task and the second task are interchangeable tasks based on the comparison, wherein interchangeable tasks share context information and belong to a common job;
executing the first task during the subsequent time slice in response to the first task and the second task being identified as interchangeable tasks;
assigning the first task and the second task to adjacent time slices in response to the first task and the second task being identified as interchangeable tasks; and
suppressing delivery of an interrupt signal at the end of the first time slice in response to the first task and the second task being identified as interchangeable tasks,
wherein the first task executes during the subsequent time slice in response to the first task and the second task being identified as interchangeable tasks.

2. The method of claim 1 , further comprising executing the second task during the subsequent time slice in response to identifying that the first task and the second task are not interchangeable tasks.

3. The method of claim 1 , wherein comparing the first task to the second task comprises comparing a first task group identifier of the first task to a second task group identifier of the second task, and wherein identifying whether the first task and the second task are interchangeable comprises determining whether the first task group identifier matches the second task group identifier.

4. The method of claim 1 , wherein identifying whether the first task and the second task are interchangeable tasks comprises identifying whether the first task and the second task belong to a common group of interchangeable tasks.

5. The method of claim 1 , further comprising:
identifying at least two interchangeable tasks scheduled to execute on the processor; and
associating an indicator with the at least two interchangeable tasks, the indicator designating that the at least two tasks are part of a common group of interchangeable tasks,
wherein identifying whether the first task and the second task are interchangeable tasks comprises evaluating the indicator to determine whether the first task and the second task are part of the group of interchangeable tasks.

6. The method of claim 5 , further comprising scheduling the at least two interchangeable tasks to adjacent time slices.

7. The method of claim 1 , wherein during a time when the first task is executing on the processor, further comprising:
receiving an interrupt signal at an end of the first time slice; and
identifying whether the first task and the second task are interchangeable in response to receiving the interrupt signal.

8. The method of claim 1 , wherein the processor is a central processing unit having a plurality of processing cores, and wherein the first task and the second task are assigned to a common processing core of the plurality of processing cores.

9. The method of claim 1 , further comprising allocating time slices equally to tasks scheduled to execute on the processor, the tasks scheduled including the first task and the second task.

10. The method of claim 1 , further comprising identifying a processor load, wherein comparing the first task to the second task occurs in response to the processor load being identified as one of moderate and heavy.

11. The method of claim 1 , further comprising:
identifying a second time slice allocated to the first task; and
executing the second task during the second time slice.

Assignees

• IBM

Inventors

• Pai Ramachandra N
• Wang Yun
• Xiao Guang Rong
• Yang Wei

Classifications

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/54 Primary

  Interprogram communication · CPC title