Preload instruction control

Patent metadata

Field	Value
Publication number	US-9632776-B2
Application number	US-201113064113-A
Country	US
Kind code	B2
Filing date	Mar 7, 2011
Priority date	Apr 22, 2010
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A processor provided with an instruction decoder responsive to preload instructions which trigger preload operations, such as page table walks and cache line fetches. An instruction decoder identifies if the memory address associated with the preload instruction matches a null value and suppresses the preload operation if the memory address does match the null value. The null value may be set under program control, it may be predetermined as a fixed value (e.g. zero) or may be set under hardware control, such as corresponding to memory addresses of a page identified by a memory management unit as non-accessible.

First claim

I claim:

1. Apparatus for processing data comprising:
processing circuitry configured to perform data processing operations in response to program instructions;
instruction decoder circuitry coupled to said processing circuitry and responsive to said program instructions to generate control signals for controlling said processing circuitry to perform said data processing operations; wherein
said instruction decoder is responsive to a preload instruction, said preload instruction specifying a memory address location to be subject to a preload operation for preparing for a subsequent memory access to said memory address, to compare said memory address with a null value and:
(i) if said memory address does not match said null value then to generate control signals for controlling said processing circuitry to perform said preload operation; and
(ii) if said memory address does match said null value then not to generate said control signals for controlling said processing circuitry to perform said preload operation.

2. Apparatus as claimed in claim 1 , comprising translation lookaside buffer circuitry configured to store address mapping data specifying translations between virtual addresses and physical addresses, wherein said memory address is a virtual memory address and said preload operation triggers loading of address mapping data for said memory address to said translation lookaside buffer if said address mapping data does not specify a translation for said memory address.

3. Apparatus as claimed in claim 2 , wherein said address mapping data for said memory address is accessible using a page table walk operation.

4. Apparatus as claimed in claim 1 , comprising a cache memory and wherein said preload operation loads data from said memory address to said cache memory.

5. Apparatus as claimed in claim 1 , wherein said null value is zero.

6. Apparatus as claimed in claim 1 , wherein said null value is one of a range of values.

7. Apparatus as claimed in claim 1 , wherein said null value is a programmable value.

8. Apparatus as claimed in claim 6 , wherein said null value is programmable by detecting circuitry configured to detect memory addresses that are not to be subject to said preload operation.

9. Apparatus as claimed in claim 1 , wherein said memory address is within a memory address space divided into memory address pages and said instruction decoder circuitry is configured to set said null value to correspond to a previously detected memory access to a non-accessible memory page.

10. Apparatus for processing data comprising:
processing means for performing data processing operations in response to program instructions;
instruction decode for generating control signals in response to said program instructions, said control signals controlling said processing means to perform said data processing operations; wherein
said instruction decode means is responsive to a preload instruction, said preload instruction specifying a memory address location to be subject to a preload operation for preparing for a subsequent memory access to said memory address, to compare said memory address with a null value and:
(i) if said memory address does not match said null value then to generate control signals for controlling said processing means to perform said preload operation; and
(ii) if said memory address does match said null value then not to generate said control signals for controlling said processing means to perform said preload operation.

11. A method of processing data comprising the steps of:
performing data processing operations in response to program instructions;
decoding program instructions to generate control signals for controlling said data processing operations; wherein
said decoding is responsive to a preload instruction, said preload instruction specifying a memory address location to be subject to a preload operation for preparing for a subsequent memory access to said memory address, to compare said memory address with a null value and:
(i) if said memory address does not match said null value then to generate control signals for controlling said data processing operations to perform said preload operation; and
(ii) if said memory address does match said null value then not to generate said control signals for controlling said data processing operations to perform said preload operation.

12. A method as claimed in claim 11 , further comprising storing address mapping data specifying translations between virtual addresses and physical addresses, wherein said memory address is a virtual memory address and said preload operation triggers loading of address mapping data for said memory address if said address mapping data does not specify a translation for said memory address.

13. A method as claimed in claim 12 , wherein said address mapping data for said memory address is accessed using a page table walk operation.

14. A method as claimed in claim 11 , wherein said preload operation loads data from said memory address to a cache memory.

15. A method as claimed in claim 11 , wherein said null value is zero.

16. A method as claimed in claim 11 , wherein said null value is one of a range of values.

17. A method as claimed in claim 11 , wherein said null value is a programmable value.

18. A method as claimed in claim 17 , wherein said null value is programmed by detecting hardware memory addresses that are not to be subject to said preload operation.

19. A method as claimed in claim 11 , wherein said memory address is within a memory address space divided into memory address pages and said null value is set to correspond to a previously detected memory access to a non-accessible memory page.

Assignees

• Craske Simon John
• Advanced Risc Mach Ltd

Inventors

• Craske Simon John

Classifications

• G06F12/0862

  with prefetch · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F9/3824 Primary

  Operand accessing · CPC title

• G06F9/383

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title