Direct digital synthesis of signals using maximum likelihood bit-stream encoding

Patent metadata

Field	Value
Publication number	US-9632750-B2
Application number	US-201514944184-A
Country	US
Kind code	B2
Filing date	Nov 17, 2015
Priority date	Oct 27, 2011
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.

First claim

What is claimed is:

1. Machine readable storage media having machine executable instructions, that when executed, cause one or more processors to perform an operation comprising:
apply an M-Algorithm to a target input signal X to perform Maximum Likelihood Sequence Estimation to produce a digital bit stream B;
filter the digital bit stream B to produce a filtered digital bit stream B; and
generate a digital stream Y from the filtered digital bit stream B, wherein the digital stream Y produces an error signal with respect to the target input signal X satisfying one or more predefined requirements.

2. The machine readable storage media of claim 1 , wherein the target input signal X comprises a desired transmit signal, and wherein the digital stream Y comprises an estimate of a desired transmit signal.

3. The machine readable storage media of claim 1 , wherein the one or more predefined requirements comprise a substantially minimum error.

4. The machine readable storage media of claim 3 , wherein the substantially minimum error comprises a difference between a digital output of an Infinite Impulse Response (IIR) filter and the target input signal X.

5. The machine readable storage media of claim 4 having machine executable instructions, that when executed, cause the one or more processors to perform an operation which comprises:
apply the digital stream Y to one or more of a switching type power amplifier and an analog restitution filter.

6. The machine readable storage media of claim 5 , wherein an output of the analog restitution filter comprises an analog RF signal that approximates the target input signal X.

7. The machine readable storage media of claim 5 , wherein the IIR filter has a frequency response that is similar to a frequency response of the analog restitution filter.

8. The machine readable storage media of claim 5 , wherein the analog restitution filter comprises one or more of:
a passive filter,
a resistive-inductive-capacitive (R-L-C) circuit; or
a transmission line.

9. The machine readable storage media of claim 4 , wherein said IIR filter comprises a passband filter and the target input signal is a baseband signal modulated to an RF frequency in a digital domain.

10. The machine readable storage media of claim 4 , wherein the IIR filter comprises a baseband filter, and wherein the target input signal X is a baseband signal.

11. The machine readable storage media of claim 4 , wherein the IIR filter is a model of a transmitter analog output channel that is to carry the digital stream Y.

12. The machine readable storage media of claim 4 , wherein the target input signal X comprises an observed analog signal, and wherein the digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream.

13. The machine readable storage media of claim 12 , wherein the BR filter is a model of an analog receive channel that the observed analog signal passed through.

14. The machine readable storage media of claim 1 , wherein the digital stream is one of: NRZ, BPSK, QPSK, or QAM modulation formats.

15. The machine readable storage media of claim 1 , wherein the maximum likelihood sequence estimation incorporates and compensates for one or more of a non-linear memory of an RF power amplifier and a digital driver analog circuit.

16. The machine readable storage media of claim 1 having machine executable instructions, that when executed, cause the one or more processors to perform an operation which comprises:
convert the generated digital stream Y to an analog signal using a transmitter of a serializer-deserializer.

17. The machine readable storage media of claim 16 , wherein the serializer-deserializer is embodied on a System on a Chip (SoC).

18. The machine readable storage media of claim 1 , wherein the maximum likelihood sequence estimation incorporates and compensates for a non-linear memory of one or more of a storage device read channel, a data channel and an analog receive channel.

19. The machine readable storage media of claim 18 , wherein bit detection is employed in the one or more of the storage device read channel and the data channel.

20. An apparatus, comprising:
a first circuitry to perform Maximum Likelihood Sequence Estimation (MLSE), the first circuitry including:
an encoder to perform MLSE to produce a digital bit stream B; and
a filter to filter the digital bit stream B, and to provide a filtered but stream B; and

a second circuitry to produce a digital stream Y from the filtered digital bit stream B, wherein the digital stream Y produces an error signal with respect to a target input signal X.

21. The apparatus of claim 20 , wherein the filter has a passband that is centered around a frequency of the target input signal X.

22. The apparatus of claim 20 , wherein the filter is one of a Finite Impulse Response (FIR) Filter or an Infinite Impulse Response (IIR) Filter.

23. The apparatus of claim 20 , wherein the MLSE is performed by applying one or more of: Viterbi scheme, Reduced State Sequence Estimation scheme, or M-algorithm.

24. The apparatus of claim 20 , wherein the first circuitry comprises a switching type power amplifier to receive the digital stream Y.

25. The apparatus of claim 20 , wherein the switching type power amplifier is a Class S amplifier.

26. The apparatus of claim 20 , wherein the first circuitry comprises an arithmetic logic to perform an operation on the filtered digital bit stream and the target input signal X.

27. The apparatus of claim 26 , wherein the arithmetic logic is an adder which is to perform a difference between the filtered digital bit stream B and the target input signal X.

28. The apparatus of claim 20 , wherein the second circuitry includes a restitution filter which is to approximate the target input signal X.

29. The apparatus of claim 28 , wherein the restitution filter comprises one or more of:
a passive filter,
a resistive-inductive-capacitive (R-L-C) circuit, or
a transmission line.

30. The apparatus of claim 28 comprises:
a transmitter of a serializer-deserializer to convert the generated digital stream Y to an analog signal.

31. The apparatus of claim 30 , wherein the serializer-deserializer is embodied on a System on a Chip (SoC).

Assignees

• Intel Corp

Inventors

• Azadet Kameran
• Pinault Steven C

Classifications

• H04L1/0054

  Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms · CPC title

• H03F2201/3209

  the amplifier comprising means for compensating memory effects · CPC title

• G06F9/3895

  for complex operations, e.g. multidimensional or interleaved address generators, macros · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• H03F3/24

  of transmitter output stages · CPC title