System and method for adaptive memory layers in a memory device

Patent metadata

Field	Value
Publication number	US-9632705-B2
Application number	US-201414573959-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Dec 17, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Systems and methods for implementing adaptive memory layers in a storage system are disclosed. A storage system may include a non-volatile memory with memory cells configurable to each of a plurality of bit-per-cell capacities and divided into dynamically re-sizable memory layers defined by memory cells of a particular capacity. A memory layer adjustment module associated with a controller of the storage system is configured to, upon detection of a maintenance trigger, compare the amount of valid data and overprovisioning in each layer to a target amount and to redistribute valid data and physical capacity among the memory layers according to a predetermined table or algorithm in order to optimize performance of each memory layer.

First claim

I claim:

1. A storage system comprising:
a nonvolatile memory having a plurality of memory cells, each of the plurality of memory cells programmable in any of a plurality of bit-per-cell capacities, the plurality of memory cells defining a plurality of memory layers, wherein each of the plurality of memory layers is defined by a portion of the plurality of memory cells currently having a same bit-per-cell capacity, and a bit-per-cell capacity of each memory layer differs from a bit-per-cell capacity of each other memory layer;
a data structure containing a predetermined target logical fullness for each of the plurality of memory layers corresponding to each of a plurality of storage system logical fullness levels; and
a controller in communication with the non-volatile memory, the controller configured to:
determine a current logical fullness of the storage system;
compare a logical fullness of one of the plurality of memory layers to a target logical fullness based on the determined logical fullness; and
in response to determining that the logical fullness of the one of the plurality of memory layers is greater than the target logical fullness:
select a block from the one of the plurality of memory layers;
copy valid data from the selected block to a different one of the plurality of memory layers; and
designate the selected block as a free block for use by any of the plurality of layers.

2. The storage system of claim 1 , wherein the non-volatile memory comprises a silicon substrate and a plurality of memory cells forming a monolithic three-dimensional structure, wherein at least one portion of the memory cells is vertically disposed with respect to the silicon substrate.

3. The storage system of claim 2 , wherein the controller is on a same substrate as the memory cells.

4. The storage system of claim 1 , where the storage system is embedded in a host.

5. The storage system of claim 1 , where the storage system is removably connectable to a host.

6. The storage system of claim 1 , wherein the predetermined target fullness differs for each of the plurality of memory layers.

7. The storage system of claim 1 , wherein the controller is further configured to determine whether a maintenance operation is needed for the storage system, and wherein the controller is configured to determine the current logical fullness of the storage system only in response to a determination that the maintenance operation is needed.

8. The storage system of claim 7 , wherein the controller is configured to determine that the maintenance operation is needed when a number of free blocks for the storage system is below a predetermined threshold.

9. The storage system of claim 1 , wherein the non-volatile memory comprises a single non-volatile memory die and each of the plurality of layers are within the single non-volatile memory die.

10. The storage system of claim 1 , wherein the non-volatile memory comprises a metadie having a plurality of individual non-volatile memory die managed as a set, and wherein each of the plurality of layers spans all of the plurality of individual non-volatile memory die in the metadie.

11. The storage system method of claim 1 , wherein to select the block the controller is configured to select a previously programmed block having a least amount of valid data in the one of the plurality of memory layers.

12. A storage system comprising:
a non-volatile memory having a plurality of memory layers, each memory layer comprising non-volatile memory cells currently programed at a same bit per cell capacity, wherein each of the plurality of memory layers has non-volatile memory cells currently programmed at a different bit-per-cell capacity than each other of the plurality of memory layers;
a memory layer distribution data structure, the memory layer distribution data structure comprising a table of predetermined target memory layer capacities corresponding to each of a plurality of storage system fullness levels; and
memory layer adjustment means:
determining a current logical fullness of the storage system;
comparing a logical fullness of one of the plurality of memory layers to a target logical fullness in the memory layer distribution data structure based on the determined logical fullness of the storage system; and
adjusting a physical capacity and a logical capacity of the one of the plurality of layers when the logical fullness of the one of the plurality of layers is greater than the target logical fullness.

13. The storage system of claim 12 , wherein to adjust the physical capacity in the one of the plurality of memory layers, the memory layer adjustment means is further configured to execute a maintenance operation in the one of the plurality of memory layers to reduce the physical capacity.

14. The storage system of claim 12 , wherein to adjust the physical and the logical capacity the memory layer adjustment means is configured to:
select a block from the one of the plurality of memory layers;
copy valid data from the selected block to the another one of the plurality of memory layers; and
identify the selected block as a free block for use by any of the plurality of layers.

15. The storage system of claim 12 , wherein the memory layer adjustment means is further configured to:
determine whether a maintenance operation is needed for the storage system; and
determine the logical fullness of the plurality of memory layers only in response to a determination that the maintenance operation is needed.

16. The storage system of claim 15 , wherein the memory layer adjustment means is further configured to determine the need for a maintenance operation in response to detecting that a number of free blocks for the storage system is below a predetermined threshold.

17. The storage system of claim 12 , wherein the non-volatile memory comprises a single non-volatile memory die and each of the plurality of layers is located within the single non-volatile memory die.

18. The storage system of claim 12 , wherein the non-volatile memory comprises a metadie having a plurality of individual non-volatile memory die managed as a set, and wherein each of the plurality of layers spans all of the plurality of individual non-volatile memory die in the metadie.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Sinclair Alan Welsh

Classifications

• G06F11/1072

  in multilevel memories · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title