Methods and systems for time keeping in a data processing system

Patent metadata

Field	Value
Publication number	US-9632563-B2
Application number	US-201414159705-A
Country	US
Kind code	B2
Filing date	Jan 21, 2014
Priority date	Jan 7, 2007
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.

First claim

What is claimed is:

1. A system, comprising:
a memory configured to store a plurality of application programs;
a processing unit configured to:
determine a time latency value for the processing unit to power up from a reduced power state;
determine a wake up time for a timed event for a given one of the stored plurality of application programs dependent upon the determined time latency value and a scheduled time for processing the timed event; and
enter the reduced power state;
and

a timer unit configured to assert, for the given one of the stored plurality of application programs, an interrupt of a first type at the determined wake up time; and
wherein the processing unit is further configured to:
in response to a determination that interrupts are disabled, convert the interrupt of the first type to an interrupt of a second type; and
exit the reduced power state in response to a determination that the interrupts have been enabled.

2. The system of claim 1 , wherein to enter the reduced power state, the processing unit is further configured to store the determined wake up time into the timer unit.

3. The system of claim 2 , wherein the interrupt of the first type has a higher priority than the interrupt of the second type.

4. The system of claim 1 , wherein the timed event includes performing one or more software instructions of the given one of the stored plurality of application programs.

5. The system of claim 1 , further comprising a plurality of functional blocks, and wherein the timed event utilizes at least one functional block of the plurality of functional blocks.

6. The system of claim 5 , wherein to determine the time latency value for the processing unit to power up from the reduced power state, the processing unit is further configured to determine the time latency value dependent upon a longest wake up latency time of the at least one functional block utilized by the timed event.

7. The system of claim 1 , wherein to determine the wake up time for the timed event, the processing unit is further configured to select the timed event from a plurality of timed events.

8. A method comprising:
determining a time latency value indicative of a time required for a processor in a system to exit from a reduced power state;
determining a wake up time for a timed event dependent upon the determined time latency value and a scheduled time for processing the timed event;
entering the reduced power state by the processor;
asserting, by a timer unit, an interrupt of a first type at the determined wake up time for the timed event;
in response to a determination that interrupts are disabled, converting, by the processor, the interrupt of the first type to an interrupt of a second type; and
exiting, by the processor, from the reduced power state in response to a determination that the interrupts have been enabled.

9. The method of claim 8 , further comprising executing one or more program instructions of an application program responsive to the processor exiting the reduced power state.

10. The method of claim 9 , wherein executing the one or more program instructions of the application program comprises utilizing at least one functional subsystem of a plurality of functional subsystems included in the system.

11. The method of claim 10 , wherein determining the time latency value further comprises selecting the time latency value dependent upon a longest time to exit the reduced power state by a functional subsystem of the plurality of functional subsystems.

12. The method of claim 8 , wherein determining the wake up time for the timed event further comprises selecting the timed event from a plurality of timed events.

13. The method of claim 10 , wherein entering the reduced power state by the processor further comprises turning off power to one or more functional subsystems of the plurality of functional subsystems responsive to a determination the one or more functional subsystems are currently idle.

14. The method of claim 8 , wherein entering the reduced power state by the processor comprises storing the determined wake up time in the timer unit.

15. An apparatus comprising:
a counter circuit; and
a processor, coupled to the counter circuit, wherein the processor is configured to:
determine a time latency value for the processor to power up from a reduced power state;
determine a wake up time for a timed event dependent upon the determined time latency value and a scheduled time for processing the timed event;
store a value into the counter circuit, wherein the value represents the determined wake up time for processing the timed event; and
enter the reduced power state;

wherein the counter circuit is configured to assert an interrupt of a first type at the determined wake up time; and
wherein the processor is further configured to
in response to a determination that interrupts are disabled, convert the interrupt of the first type to an interrupt of a second type; and
exit from the reduced power state in response to a determination that the interrupts have been enabled.

16. The apparatus of claim 15 , wherein the processor is further configured to execute one or more program instructions of an application program responsive to exiting from the reduced power state.

17. The apparatus of claim 16 , wherein the apparatus further comprises a plurality of functional subsystems, and wherein to execute the one or more program instructions, the processor is further configured to utilize at least one functional subsystem of the plurality of functional subsystems.

18. The apparatus of claim 17 , wherein to determine the time latency value for the processor to power up from the reduced power state, the processor is further configured to select the time latency value dependent upon a longest time to exit the reduced power state of the at least one functional subsystem.

19. The apparatus of claim 17 , wherein to enter the reduced power state, the processor is further configured to turn off power to one or more functional subsystems of the plurality of functional subsystems responsive to a determination the one or more functional subsystems are currently idle.

20. The apparatus of claim 15 , wherein to determine the wake up time for the timed event, the processor is further configured to select the timed event from a plurality of timed events.

Assignees

• Apple Inc

Inventors

• De Cesare Joshua P
• Semeria Bernard Joseph
• Smith Michael John

Classifications

• G06F9/4825 Primary

  Interrupt from clock, e.g. time of day · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• Y02B60/144

  Cross-Sectional Technologies · mapped topic

• G06F13/36

  for access to common bus or bus system · CPC title