Array substrate comprising a barrier layer pattern and the method for manufacturing the same, and liquid crystal display device

Patent metadata

Field	Value
Publication number	US-9632382-B2
Application number	US-201314105600-A
Country	US
Kind code	B2
Filing date	Dec 13, 2013
Priority date	Dec 14, 2012
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

The example of present invention provides an array substrate, the method for manufacturing the same, and a liquid crystal display device, wherein the array substrate comprises: a gate electrode, a gate insulating layer, a barrier layer pattern and an active semiconductor layer pattern formed by metal oxide semiconductor which are located on the gate insulating layer, a semiconductor protecting layer which covers the barrier layer pattern and the active semiconductor layer pattern, and has via holes at positions corresponding to the barrier layer pattern and the active semiconductor layer pattern; a data wire, a source electrode and a drain electrode formed by metal Cu, which are located at via holes. Metal Cu is used to form the data wire, the source electrode and the drain electrode, and the metal oxide semiconductor is used as the barrier layer for the metal Cu, and as a result, the diffusion of metal Cu into the layers such as the gate insulating layer etc., is prevented in the manufacturing process of TFT.

First claim

What is claimed is:

1. An array substrate, comprising:
a gate electrode;
a gate insulating layer;
a barrier layer pattern and an active semiconductor layer pattern, with each of the barrier layer pattern and an active semiconductor layer pattern being formed of a metal oxide semiconductor and being directly located on the top surface of the gate insulating layer, and wherein the barrier layer pattern is configured to increase an adhesion of metal Cu thin film and prevent metal Cu ion diffusing into the gate insulating layer;
a semiconductor protecting layer, configured to cover the barrier layer pattern and the active semiconductor layer pattern, with via holes being formed in the semiconductor protecting layer and at top surface of the barrier layer pattern and the active semiconductor layer pattern; and
a data wire, a source electrode and a drain electrode made of metal Cu, wherein the data wire connects to the barrier layer pattern through metal Cu in a corresponding via hole, the source electrode and the drain electrode connect to the active semiconductor layer pattern through metal Cu in corresponding via holes respectively,
wherein the data wire fills the data wire corresponding via hole, the source electrode fills the source electrode corresponding via hole and the drain electrode fills the drain electrode corresponding via hole.

2. The array substrate according to claim 1 , wherein, the gate insulating layer includes two layers, the first layer is a silicon nitride layer and the second layer is a silicon oxide layer which contacts the active semiconductor layer pattern or the semiconductor protecting layer directly.

3. The array substrate according to claim 1 , wherein, the semiconductor protecting layer includes two layers, the first layer is a silicon nitride layer and the second layer is an oxide layer, the oxide layer is a metal oxide layer or a silicon oxide layer, the first layer contacts the active semiconductor layer pattern directly.

4. The array substrate according to claim 1 , wherein, a transparent conductive material is used to form a connecting wire between data wire and source electrode, the connecting wire between data wire and source electrode connects the data wire and the source electrode at a connecting via hole of data wire and source electrode.

5. The array substrate according to claim 1 , wherein,
a thin film is formed by a transparent conductive material at a source electrode via hole, to cover the source electrode at the source electrode via hole.

6. The array substrate according to claim 1 , characterized in that,
a thin film is formed by a transparent conductive material at a drain electrode via hole, to cover the drain electrode at the drain electrode via hole.

7. A method for manufacturing an array substrate, wherein the array substrate comprises:
a gate electrode;
a gate insulating layer;
a barrier layer pattern and an active semiconductor layer pattern, with each of the barrier layer pattern and an active semiconductor layer pattern being formed of a metal oxide semiconductor and being directly located on the top surface of the gate insulating layer, and wherein the barrier layer pattern is configured to increase an adhesion of metal Cu thin film and prevent metal Cu ion diffusing into the gate insulating layer;
a semiconductor protecting layer, configured to cover the barrier layer pattern and the active semiconductor layer pattern, with via holes being formed in the semiconductor protecting layer and at top surface of the barrier layer pattern and the active semiconductor layer pattern; and
a data wire, a source electrode and a drain electrode made of metal Cu, wherein the data wire connects to the barrier layer pattern through metal Cu in a corresponding via hole, the source electrode and the drain electrode connect to the active semiconductor layer pattern through metal Cu in corresponding via holes respectively,
wherein the data wire fills the data wire corresponding via hole, the source electrode fills the source electrode corresponding via hole and the drain electrode fills the drain electrode corresponding via hole, and
wherein the method comprises:
forming the gate electrode and a gate electrode scanning line through a one-time patterning process;
forming the gate insulating layer;
forming the barrier layer pattern and the active semiconductor layer pattern of metal oxide semiconductor through a one-time patterning process;
forming the semiconductor protecting layer with via holes through a one-time patterning process;
forming patterns of data wire, the source electrode and the drain electrode made of metal Cu through a one-time patterning process, wherein, the data wire connects to the barrier layer pattern through metal Cu in a corresponding via hole, and the source electrode and the drain electrode connect to the active semiconductor layer pattern through metal Cu in corresponding via holes respectively; and
forming a connecting wire between data wire and source electrode, and a transparent pixel electrode through a one-time patterning process.

8. The method according to claim 7 , wherein, said via holes are formed at positions corresponding to the barrier layer pattern and the active semiconductor layer pattern.

9. The method according to claim 7 , the step of forming a connecting wire between data wire and source electrode, and a transparent pixel electrode through a patterning process further comprising:
a transparent conductive material being used to form the connecting wire between data wire and source electrode, the connecting wire between data wire and source electrode connecting the data wire and the source electrode at a connecting via hole of data wire and source electrode.

10. A liquid crystal display device, comprising the array substrate of claim 1 .

11. The liquid crystal display device according to claim 10 , wherein, the gate insulating layer includes two layers, the first layer is a silicon nitride layer and the second layer is a silicon oxide layer which contacts the active semiconductor layer pattern or the semiconductor protecting layer directly.

12. The liquid crystal display device according to claim 10 , wherein, the semiconductor protecting layer includes two layers, the first layer is a silicon nitride layer and the second layer is an oxide layer, the oxide layer is a metal oxide layer or a silicon oxide layer, the first layer contacts the active semiconductor layer pattern directly.

13. The liquid crystal display device according to claim 10 , wherein, a transparent conductive material is used to form a connecting wire between data wire and source electrode, the connecting wire between data wire and source electrode connects the data wire and the source electrode at a connecting via hole of data wire and source electrode.

14. The liquid crystal display device according to claim 10 , wherein,
a thin film is formed by a transparent conductive material at a source electrode via hole, to cover the source electrode at the source electrode via hole.

15. The liquid crystal display device according to claim 10 , characterized in that,
a thin film is formed by a transparent conductive material at a drain electrode via hole, to cover the drain electrode at the drain electrode via hole.

16. An array substrate, comprising:
a gate electrode;
a gate insulating layer;
a barrier layer pattern and an active semiconductor layer pattern, each of the barrier layer pattern and an active semiconductor layer being formed of a metal oxide semiconductor and being located on the same surface of the gate insulating laye

Assignees

• Boe Technology Group Co Ltd

Inventors

• Liu Xiang

Classifications

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H01L27/1251

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic

• H01L27/127

  Electricity · mapped topic