Method of manufacturing glass component, glass component, and glass interposer

US9629250B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9629250-B2
Application numberUS-201514679237-A
CountryUS
Kind codeB2
Filing dateApr 6, 2015
Priority dateApr 28, 2014
Publication dateApr 18, 2017
Grant dateApr 18, 2017

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of manufacturing a glass component includes preparing a glass substrate having a thickness greater than or equal to 300 μm, forming first electric wires on a first surface of the glass substrate, forming a structure by joining the glass substrate via a resin layer to a support substrate such that the first surface of the glass substrate faces the resin layer, thinning the glass substrate from a second surface of the glass substrate to a thickness between 10 μm and 80 μm, forming through holes in the glass substrate by irradiating the glass substrate from the second surface with a laser beam, forming second electric wires on the second surface of the glass substrate such that the second electric wires are electrically connected to the corresponding first electric wires via conductors filling the through holes, and separating the glass substrate from the support substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a glass component, the method comprising in the following order: preparing a glass substrate including a first surface and a second surface and having a thickness of at least 300 μm; forming first electric wires on the first surface of the glass substrate; forming a structure by joining the glass substrate via a resin layer to a support substrate such that the first surface of the glass substrate, which has the first electric wires on the first surface, faces the resin layer; thinning the glass substrate from the second surface towards the first surface to a thickness of from 10 μm to 80 μm; forming through holes in the glass substrate by irradiating the glass substrate from the second surface with a laser beam; forming second electric wires on the second surface of the glass substrate such that the second electric wires are electrically connected to the corresponding first electric wires via conductors filling the through holes; separating the glass substrate from the support substrate; and cutting the glass component at predetermined positions in a vertical direction after forming the second electric wires and before or after separating the glass substrate from the support substrate, thereby obtaining glass components each comprising a first electric wire of the formed first electric wires and a corresponding second electric wire of the formed second electric wires. 2. The method as claimed in claim 1 , wherein the forming of the first electric wires comprises: forming a first seed layer on the first surface of the glass substrate; forming a first conductive layer on the first seed layer; and patterning the first seed layer and the first conductive layer disposed on the first surface. 3. The method as claimed in claim 1 , wherein the forming of the second electric wires comprises forming a second seed layer on the second surface of the glass substrate; forming a second conductive layer on the second seed layer; and patterning the second seed layer and the second conductive layer disposed on the second surface. 4. The method as claimed in claim 1 , wherein the first electric wires are formed to have a width of from 2 μm to 5 μm. 5. The method as claimed in claim 1 , wherein the second electric wires are formed to have a width of from 2 μm to 5 μm. 6. The method as claimed in claim 1 , wherein the glass substrate is thinned by selectively etching the second surface. 7. The method as claimed in claim 1 , wherein the through holes are filled with the conductors comprised of a material that is the same as a material of the second electric wires. 8. The method as claimed in claim 1 , wherein the through holes are formed so as not to pass through the first electric wires. 9. The method as claimed in claim 1 , wherein the first electric wires are embedded into the resin layer. 10. The method as claimed in claim 2 , wherein the through holes do not pass through the first conductive layer of the first wires.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • by a laser beam · CPC title

  • Joining pieces of glass to pieces of other inorganic material; Joining glass to glass other than by fusing (C03C17/00 takes precedence; layered structures comprising at least one glass sheet B32B17/00; wired glass C03B; joining glass to ceramics C04) · CPC title

  • Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

  • Drilling of holes · CPC title

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Frequently asked questions

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What does patent US9629250B2 cover?
A method of manufacturing a glass component includes preparing a glass substrate having a thickness greater than or equal to 300 μm, forming first electric wires on a first surface of the glass substrate, forming a structure by joining the glass substrate via a resin layer to a support substrate such that the first surface of the glass substrate faces the resin layer, thinning the glass substra…
Who is the assignee on this patent?
Asahi Glass Co Ltd
What technology area does this patent fall under?
Primary CPC classification H05K3/007. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).