Transformer feedback amplifier

Patent metadata

Field	Value
Publication number	US-9628031-B2
Application number	US-201514643640-A
Country	US
Kind code	B2
Filing date	Mar 10, 2015
Priority date	Oct 29, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

An apparatus includes: first and second transistors, each of the first and second transistors includes a gate terminal, a source terminal, and a drain terminal; and a transformer including a primary winding and first and second secondary windings, the primary winding is coupled to a first input node configured to receive an input signal and a second input node configured to receive a potential, the first and second secondary windings are coupled to gate terminals of the first and second transistors and cross-coupled to source terminals of the first and second transistors.

First claim

What is claimed is:

1. An apparatus comprising:
first and second transistors, each of the first and second transistors includes a gate terminal, a source terminal, and a drain terminal;
a transformer including a primary winding and first and second secondary windings,
the primary winding is coupled to a first input node configured to receive an input signal and a second input node configured to receive a potential,
the first and second secondary windings are coupled to gate terminals of the first and second transistors and cross-coupled to source terminals of the first and second transistors; and
a first switch disposed between the first input node and a first input terminal of the primary winding, the first switch configured to pass the input signal to the first input terminal of the primary winding.

2. The apparatus of claim 1 , further comprising:
first and second bias resistors coupled to the gate terminals of the first and second transistors, respectively; and
a controller configured to bias the first and second transistors into a low linearity mode using the first and second bias resistors.

3. The apparatus of claim 1 , the first secondary winding is coupled to the gate terminal of the first transistor and the source terminal of the second transistor, and second secondary winding is coupled to the source terminal of the first transistor and the gate terminal of the second transistor.

4. The apparatus of claim 1 , further comprising
third and fourth transistors coupled to the first and second transistors, each of the third and fourth transistors includes a gate terminal, a source terminal, and a drain terminal.

5. The apparatus of claim 4 , the drain terminal of the third transistor is coupled to the drain terminal of the first transistor and the drain terminal of the fourth transistor is coupled to the drain terminal of the second transistor.

6. The apparatus of claim 4 , the first and second secondary windings are coupled to gate terminals of the third and fourth transistors and cross coupled to source terminals of the third and fourth transistors.

7. The apparatus of claim 4 , further comprising:
third and fourth bias resistors coupled to the gate terminals of the third and fourth transistors, respectively; and
a controller coupled to the third and fourth bias resistors and configured to bias the third and fourth transistors into a high linearity mode.

8. The apparatus of claim 4 , further comprising
a variable capacitor coupled to the gate terminals of the first, second, third, and fourth transistors.

9. The apparatus of claim 1 , further comprising
a second switch disposed between the first input terminal of the primary winding and a ground voltage, the second switch configured to short the first input terminal of the primary winding.

10. The apparatus of claim 1 , further comprising
a third switch disposed between the second input node and a second input terminal of the primary winding, the third switch configured to pass the potential that is a negative signal with respect to the input signal to form a differential signal with the input signal.

11. The apparatus of claim 10 , further comprising
a fourth switch disposed between the second input terminal of the primary winding and a ground voltage, the fourth switch configured to short the second input terminal of the primary winding.

12. The apparatus of claim 1 , further comprising:
third and fourth transistors coupled to the first and second transistors; and
a controller configured to substantially bias the first and second transistors into a low linearity mode and bias the third and fourth transistors to discharge a small amount of bias current during the low linearity mode.

13. The apparatus of claim 1 , further comprising:
third and fourth transistors coupled to the first and second transistors; and
a controller configured to substantially bias the third and fourth transistors into a high linearity mode and bias the first and second transistors to discharge a small amount of bias current during the high linearity mode.

14. An apparatus comprising:
first and second means for amplifying, each of the first and second means for amplifying includes at least an input terminal and an output terminal;
means for receiving an input signal and a potential;
means for transferring energy including a primary winding and first and second secondary windings,
the primary winding coupled to the means for receiving an input signal and the means for receiving a potential,
the first and second secondary windings are coupled to input terminals of the first and second means for amplifying and cross-coupled to output terminals of the first and second means for amplifying; and
third and fourth means for amplifying coupled to the first and second means for amplifying, each of the third and fourth means for amplifying includes an input terminal and an output terminal,
wherein the first and second secondary windings are also coupled to input terminals of the third and fourth means for amplifying and cross-coupled to output terminals of the third and fourth means for amplifying.

15. The apparatus of claim 14 , further comprising
means for biasing the first and second means for amplifying into a low linearity mode.

16. The apparatus of claim 14 , further comprising
means for controlling configured to substantially bias the first and second means for amplifying into a low linearity mode and bias the third and fourth means for amplifying to discharge a small amount of bias current during the low linearity mode.

17. The apparatus of claim 14 , further comprising
means for controlling configured to substantially bias the third and fourth means for amplifying into a high linearity mode and bias the first and second means for amplifying to discharge a small amount of bias current during the high linearity mode.

18. An apparatus comprising:
first and second transistors, each of the first and second transistors includes a gate terminal, a source terminal, and a drain terminal;
a transformer including a primary winding and first and second secondary windings,
the primary winding is coupled to a first input node configured to receive an input signal and a second input node configured to receive a potential,
the first and second secondary windings are coupled to gate terminals of the first and second transistors and cross-coupled to source terminals of the first and second transistors; and
third and fourth transistors coupled to the first and second transistors, each of the third and fourth transistors includes a gate terminal, a source terminal, and a drain terminal,
the first and second secondary windings are coupled to gate terminals of the third and fourth transistors and cross coupled to source terminals of the third and fourth transistors.

19. The apparatus of claim 18 , further comprising:
first and second bias resistors coupled to the gate terminals of the first and second transistors, respectively; and
a controller configured to bias the first and second transistors into a low linearity mode using the first and second bias resistors.

20. The apparatus of claim 18 , the drain terminal of the third transistor is coupled to the drain terminal of the first transistor and the drain terminal of the fourth transistor is coupled to the drain terminal of the second transistor.

21. The apparatus of claim 18 , further comprising:
third and fourth bias resistors coupled to the gate terminals of the third and fourth

Assignees

• Qualcomm Inc

Inventors

• Choksi Ojas Mahendra
• Fan Bin
• Hanafi Bassel

Classifications

• H03F2203/45306

  the common gate stage implemented as dif amp eventually for cascode dif amp · CPC title

• H03F2203/45616

  the IC comprising more than one switch, which are not cross coupled · CPC title

• H03F2203/45318

  the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled · CPC title

• H03F1/565 Primary

  using inductive elements · CPC title

• H03F3/45071

  with semiconductor devices only · CPC title