Power converter package structure and method

Patent metadata

Field	Value
Publication number	US-9627972-B2
Application number	US-201514728590-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Jun 8, 2011
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

An embodiment power converter package comprises a semiconductor die, an output inductor, a plurality of input capacitors and output capacitors. The semiconductor die, the output inductor and the plurality of capacitors are mounted on a lead frame and connected one to another through various pads on the lead frame. The semiconductor die comprises a high side switch, a low side switch and a driver. The power converter package is electrically coupled to an external pulse width modulation controller through a variety of input and output pads.

First claim

What is claimed is:

1. A system comprising:
a plurality of power blocks, each of which comprises:
a first semiconductor die mounted on a lead frame, wherein the first semiconductor die is electrically coupled to a regulator controller located outside the power block, wherein the first semiconductor die comprises:
a high side switch comprising:
a first drain coupled to a plurality of input capacitors;
a first gate coupled to a driver; and
a first source;

a low side switch comprising:
a second drain coupled to the first source;
a second gate coupled to the driver; and
a second source coupled to ground; and

the driver comprising:
an input terminal coupled to the regulator controller; and
various outputs coupled to the high side switch and the low side switch;

an inductor mounted on the lead frame, wherein the inductor is coupled to the first semiconductor die through a plurality of power pads on the lead frame;
the plurality of input capacitors mounted on the lead frame, wherein the plurality of input capacitors are coupled to the first semiconductor die; and
a plurality of output capacitors mounted on the lead frame, wherein the plurality of output capacitors are coupled to the first semiconductor die; and

the regulator controller coupled to the plurality of power blocks.

2. The system of claim 1 , further comprising:
a resistor connected between two signal inputs of the first semiconductor die.

3. The system of claim 2 , wherein:
the resistor is configured such that a delay between two gate drive signals of a buck converter embedded in the first semiconductor die is adjustable based upon a resistance value of the resistor.

4. The system of claim 1 , wherein:
the first semiconductor die comprises a first signal output reporting a current flowing through a buck converter embedded in the first semiconductor die.

5. The system of claim 1 , wherein:
the first semiconductor die comprises a second signal output reporting a junction temperature of the first semiconductor die.

6. The system of claim 1 , further comprising:
an ON/OFF signal wherein the ON/OFF signal is configured such that:
the first semiconductor die is controlled by the regulator controller when the ON/OFF signal is enabled; and
the first semiconductor die operates in an inactive mode when the ON/OFF signal is disabled.

7. The system of claim 1 , wherein:
the first semiconductor die receives a variety of control singles from the regulator controller.

8. A system comprising:
a plurality of power blocks coupled between a bus voltage and a load, wherein:
each power block has at least one input coupled to a controller; and
each power block comprises a semiconductor die mounted on a lead frame, an inductor mounted on the lead frame, a plurality of input capacitors mounted on the lead frame and a plurality of output capacitors mounted on the lead frame, wherein the input capacitors are placed between two terminals of the bus voltage and the output capacitors are placed between two terminals of the load, wherein each power block comprises:

a high side switch comprising:
a first drain coupled to the plurality of input capacitors;
a first gate coupled to a driver; and
a first source;

a low side switch comprising:
a second drain coupled to the first source;
a second gate coupled to the driver; and
a second source coupled to ground; and

the driver comprising:
an input terminal coupled to the controller; and
various outputs coupled to the high side switch and the low side switch.

9. The system of claim 8 , wherein:
the semiconductor die is electrically coupled to the controller; and
the inductor is coupled to the semiconductor die through a plurality of power pads on the lead frame.

10. The system of claim 8 , wherein:
the high side switch, the low side switch and the inductor form a step-down converter.

11. The system of claim 8 , wherein:
outputs of the plurality of power blocks are stacked together to achieve a higher output voltage.

12. The system of claim 8 , wherein:
the plurality of power blocks are configured to operate in parallel.

13. The system of claim 8 , wherein:
the controller is located outside the lead frame; and
each power block is attached to the lead frame through a plurality of solder bumps.

14. A system comprising:
a plurality of power blocks, each of which is a lead frame and comprises:
a first semiconductor die electrically coupled to a regulator controller, wherein the first semiconductor die comprises:
a high side switch comprising:
a first drain coupled to a plurality of input capacitors;
a first gate coupled to a driver; and
a first source;

a low side switch comprising:
a second drain coupled to the first source;
a second gate coupled to the driver; and
a second source coupled to ground; and

the driver comprising:
an input terminal coupled to the regulator controller; and
various outputs coupled to the high side switch and the low side switch;

an inductor coupled to the first semiconductor die through a plurality of power pads on the lead frame, wherein a ground trace is between two pads directly connected to the inductor;
the plurality of input capacitors mounted on the lead frame and placed between two terminals of an input power source; and
a plurality of output capacitors mounted on the lead frame and placed between two terminals of a load; and

a controller coupled to the plurality of power blocks, wherein the controller is outside the lead frame.

15. The system of claim 14 , wherein:
each power block is a buck converter.

16. The system of claim 14 , wherein:
negative terminals of the plurality of input capacitors and negative terminals of the plurality of output capacitors share a same pad on the lead frame.

17. The system of claim 14 , wherein:
an L-shaped portion of a ground pad is underneath the inductor.

18. The system of claim 14 , wherein:
an output pad Vo is an L-shaped pad.

19. The system of claim 18 , wherein:
the output pad Vo and an input pad Vin are separated by a ground pad.

Assignees

• Futurewei Technologies Inc

Inventors

• Mao Hengchun
• Fu Dianbo
• Cai Bing

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/072

  of bump connectors · CPC title