Memory system having overwrite operation control method thereof

Patent metadata

Field	Value
Publication number	US-9627388-B2
Application number	US-201514731003-A
Country	US
Kind code	B2
Filing date	Jun 4, 2015
Priority date	Jun 11, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

The memory system has an overwrite operation and an operation control method thereof. A nonvolatile memory device has a plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to a substrate. When data of memory cells connected to a word line of a selected memory block is read, the need of reclaim is determined based on an error bit level of the read data. In the case that memory cells having an erase state among the memory cells connected to the word line become a soft program state, the read data is overwritten in the memory cells connected to the word line of the selected memory block.

First claim

What is claimed is:

1. A method of controlling a nonvolatile memory device having a plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to a substrate, the method comprising:
reading data of memory cells connected to a word line of a selected memory block;
determining a need of reclaim based on an error bit level of the read data; and
checking a soft program state level with respect to the memory cells connected to the word line, and then performing an overwrite operation including overwriting the read data in the memory cells connected to the word line of the selected memory block in the case that it is determined that the soft program state level does not go beyond a first setting range.

2. The method of controlling a nonvolatile memory device of claim 1 , wherein a read of the soft program state is performed on memory cells having an erase state among the memory cells connected to the word line.

3. The method of controlling a nonvolatile memory device of claim 1 , further comprising, in the case that it is determined that the soft program state level goes beyond the first setting range and exists in a second setting range, soft-erasing the memory cells connected to the word line before overwriting the read data.

4. The method of controlling a nonvolatile memory device of claim 3 , further comprising, in the case that the soft program state level goes beyond the second setting range, writing the read data in a different memory block from the selected memory block.

5. The method of controlling a nonvolatile memory device of claim 1 , wherein in the overwrite operation, the read data being overwritten in the memory cells is error corrected data.

6. The method of controlling a nonvolatile memory device of claim 1 , wherein the nonvolatile memory device comprises a memory cell array defining a three-dimensional NAND flash memory device.

7. The method of controlling a nonvolatile memory device of claim 1 , wherein the overwrite operation is performed by a full page program of a memory block unit.

8. The method of controlling a nonvolatile memory device of claim 1 , wherein the overwrite operation is performed by a full page program of a word line unit.

9. The method of controlling a nonvolatile memory device of claim 1 , wherein the memory cells comprise multi-level cells storing two or more bits.

10. The method of controlling a nonvolatile memory device of claim 1 , wherein an error bit level of the read data, when determining the need of reclaim, is within the error correcting code (ECC) error correctable range.

11. A method of controlling a nonvolatile memory device having a plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to a substrate, the method comprising:
reading data written in memory cells connected to a word line of a first memory block;
determining a need of reclaim based on an error bit level of the read data;
checking a soft program state level with respect to memory cells having an erase state among memory cells connected to the word line, and then performing an overwrite operation by directly overwriting the read data in the memory cells connected to the word line of the first memory block in the case that it is determined that the soft program state level is within a first setting range; and
writing the read data in a second memory block different from the first memory block in the case that it is determined that the soft program state level goes beyond the first setting range.

12. The method of controlling a nonvolatile memory device of claim 11 , further comprising, in the case that it is determined that the soft program state level does not go beyond a first setting range by a specific range and is within the specific range, performing a soft erase operation before overwriting the read data in the memory cells.

13. The method of controlling a nonvolatile memory device of claim 11 , wherein in the overwrite operation, the data being stored in the memory cells is error corrected data.

14. The method of controlling a nonvolatile memory device of claim 11 , wherein in the overwrite operation, the read data is overwritten in the memory cells connected to the word line of the first memory block as it is, and a mapping table of mapping a physical address corresponding to a logical address of the first memory block remains unchanged.

15. The method of controlling a nonvolatile memory device of claim 11 , wherein in a reclaim process of writing the read data in a second memory block different from the first memory block, as the read data moves to the second memory block different from the first memory block, a mapping table of mapping a physical address corresponding to a logical address of the first memory block is changed.

16. A memory system comprising:
a nonvolatile memory device having a plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to a substrate; and
a memory controller having an overwriting manager;
wherein when data stored in memory cells connected to a selected word line of one memory block of the memory blocks is read to the memory controller and it is determined that an error bit level of the read data needs a reclaim and if a soft program state level of the memory cells connected to the word line is checked and it is determined that the soft program state level is within a specific range, the overwriting manager controls the read data to be overwritten in the memory cells connected to the word line of the selected memory block.

17. The memory system of claim 16 , wherein checking the soft program state level is performed on memory cells having an erase state among memory cells connected to the word line; and wherein the overwriting manager performs overwriting on memory cells having a program state among memory cells connected to the word line.

18. The memory system of claim 16 , wherein the data being overwritten in the memory cells is data error-corrected by an error correction code (ECC) decoding operation.

19. The memory system of claim 16 , wherein when the soft program state level is out of a specific range as a result of the check, the read data is written in a fresh memory block different from the selected memory block.

20. The memory system of claim 16 , wherein in the case that the memory cells are multi level cells storing two or more bits, the overwrite operation includes performing a last page program on a word line of the memory cells.

Assignees

• Kang Hee-Woong
• Kim Suejin
• Lee Heewon
• Samsung Electronics Co Ltd

Inventors

• Kang Hee-Woong
• Kim Suejin
• Lee Heewon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C11/5635 Primary

  Erasing circuits · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title