Semiconductor device with active fins separated by shallow and deep trench isolations and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9627376-B2
Application number	US-201414281224-A
Country	US
Kind code	B2
Filing date	May 19, 2014
Priority date	Jun 21, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A semiconductor device includes first and second memory cell regions adjacent to each other on a substrate. At least one active base and a shallow trench isolation may be sequentially laminated at a boundary between the first and second memory cell regions. First and second active fins are formed on respective sides of the shallow trench isolation, and the first and second active fins projecting from the active base. At least one deep trench isolation is formed on one side of the active base.

First claim

What is claimed is:

1. A semiconductor device, comprising:
first and second memory cells and adjacent to each other with no intervening memory cell on a substrate, wherein each of the first and second memory cells have an odd number of active fins;
at least one active base and a shallow trench isolation sequentially laminated at a boundary between the first and second memory cells;
first and second active fins on respective sides of the shallow trench isolation, the first and second active fins projecting from the active base;
a gate electrode; and
at least one deep trench isolation on one side of the active base,
wherein the first active fin is in the first memory cell and the second active fin is in the second memory cell, wherein the first and second active fins extend in a first direction along the boundary between the first and second memory cells, and wherein the gate electrode extends from the first and second active fins in a second direction that crosses the first direction, wherein the first and second memory cells are symmetrically arranged with respect to each other relative to the boundary.

2. The semiconductor device as claimed in claim 1 , wherein a width of the active base is larger than a width of each of the first and second active fins.

3. The semiconductor device as claimed in claim 2 , further comprising:
a plurality of active bases,
wherein the first and second active fins are separated by the shallow trench isolation, and wherein at least two of the plurality of active bases are separated by the deep trench isolation.

4. The semiconductor device as claimed in claim 1 , further comprising:
a gate insulating film between the gate electrode and the first and second active fins; and
a spacer on at least one side of the gate electrode, wherein the gate insulating film extends along a side wall of the spacer.

5. The semiconductor device as claimed in claim 4 , wherein the gate electrode includes a gate metal and a work function metal.

6. The semiconductor device as claimed in claim 4 , further comprising:
a source region and a drain region respectively formed on the first and second active fins adjacent to the gate electrode, wherein upper surfaces of the source region and the drain region are higher than a lower surface of the gate insulating film.

7. The semiconductor device as claimed in claim 6 , wherein a part of at least one of the source region or the drain region is adjacent to a lower portion of the spacer.

8. The semiconductor device as claimed in claim 1 , wherein the substrate is an insulating substrate.

9. The semiconductor device as claimed in claim 1 , wherein a same type of memory device is included in the first memory cell and in the second memory cell.

10. The semiconductor device as claimed in claim 9 , wherein the memory device includes a static random access memory.

Assignees

• Song Tae-Joong
• Park Jae-Ho
• Baek Kang-Hyun
• Samsung Electronics Co Ltd

Inventors

• Song Tae-Joong
• Park Jae-Ho
• Baek Kang-Hyun

Classifications

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D62/113

  Isolations within a component, i.e. internal isolations · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/6681

  Electricity · mapped topic

• H01L27/1211

  Electricity · mapped topic