Stacked memory allowing variance in device interconnects

Patent metadata

Field	Value
Publication number	US-9627357-B2
Application number	US-201113997152-A
Country	US
Kind code	B2
Filing date	Dec 2, 2011
Priority date	Dec 2, 2011
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

First claim

What is claimed is:

1. A memory device comprising:
a system element for the memory device, the system element including a plurality of pads; and
a memory stack connected with the system element, the memory stack including one or more memory die layers, a connection of the system element and the memory stack including a plurality of interconnects for connecting a first memory die layer and the plurality of pads of the system element;
wherein for a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, wherein the first subset of the plurality of pads are spaced such that at least one pad is located between each pad of the first subset of pads; and
wherein for two or more memory die layers in the memory stack, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

2. The memory device of claim 1 , wherein the single memory die layer is the sole memory die layer in the memory stack, and wherein a first pitch of interconnect is used for the interconnects of the first memory die layer and the system element.

3. The memory device of claim 1 , wherein two or more memory die layers are present in the memory stack and wherein a second pitch of interconnect is used for the interconnects of the first memory die layer and the system element, a first pitch of interconnect used for a sole memory die layer being greater than the second pitch of interconnect.

4. The memory device of claim 1 , wherein the memory device is structured for a subset of a total logic memory interconnect between the memory stack and the system element of the memory device to be driven from each memory die layer.

5. The memory device of claim 1 , wherein the number of memory die layers is a maximum number of memory die layers for the memory stack, and wherein all of the pads of the plurality of pads are used for interconnects.

6. The memory device of claim 1 , wherein the system element is a system on chip (SoC).

7. A system comprising:
a bus;
a stacked memory device coupled to the bus; and
a processor coupled to the bus, the processor to read data from and write data to the stacked memory device;
wherein the stacked memory device includes:
a system element for the stacked memory device, the system element including a plurality of pads, and
a memory stack connected with the system element, the memory stack including one or more memory die layers, a connection of the system element and the memory stack including a plurality of interconnects for connecting a first memory die layer and the plurality of pads of the system element;

wherein for a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, wherein the first subset of the plurality of pads are spaced such that at least one pad is located between each pad of the first subset of pads; and
wherein for two or more memory die layers in the memory stack, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

8. The system of claim 7 , wherein the single memory die layer is the sole memory die layer in the memory stack, and wherein a first pitch of interconnect is used for the interconnects between the first memory die layer and the system element.

9. The system of claim 7 , wherein two or more die layers are present in the memory stack and wherein a second pitch of interconnect is used for the interconnects if a certain number of memory die layers are present in the memory stack, the certain number being two or greater, a first pitch of interconnect used for a sole memory die layer being greater than the second pitch of interconnect.

10. The system of claim 7 , wherein the memory device is structured for a subset of a total logic memory interconnect between the memory stack and the system element of the memory device to be driven from each memory die layer.

11. A memory device comprising:
a system element for the memory device, the system element including a plurality of pads;
a memory stack connected with the system element, the memory stack including one or more memory die layers, a connection of the system element and the memory stack including a plurality of interconnects for connecting a first memory die layer and the plurality of pads of the system element; and
a silicon interposer, the connection including a coupling of the system element and memory stack to the silicon interposer;
wherein for a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack; and
wherein for two or more memory die layers in the memory stack, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

12. A memory device comprising:
a system element for the memory device, the system element including a plurality of pads;
a memory stack connected with the system element, the memory stack including one or more memory die layers, a connection of the system element and the memory stack including a plurality of interconnects for connecting a first memory die layer and the plurality of pads of the system element; and
a non-silicon package substrate, the memory stack including a single memory die layer, and the connection including a coupling of the system element and the single memory die layer to the non-silicon package substrate;
wherein for a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack; and
wherein for two or more memory die layers in the memory stack, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

Assignees

• Shoemaker Kenneth
• Vogt Pete
• Intel Corp

Inventors

• Shoemaker Kenneth
• Vogt Pete

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title