Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9627350-B2
Application number	US-201514959139-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Apr 30, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method for manufacturing a semiconductor device according to the present invention includes: (a) disposing, on a substrate (insulating substrate), a bonding material having a sheet shape and having sinterability; (b) disposing a semiconductor element on the bonding material after the (a); and (c) sintering the bonding material while applying pressure to the bonding material between the substrate and the semiconductor element. The bonding material includes particles of Ag or Cu, and the particles are coated with an organic film.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
(a) disposing, on a substrate, a bonding material cut-out of a sheet using an adsorptive collet and having sinterability;
(b) disposing a semiconductor element on said bonding material after said (a); and
(c) sintering said bonding material while applying pressure to said bonding material between said substrate and said semiconductor element,
wherein said bonding material includes only particles of one of Ag, Au, Pd, Pt, Cu, or other noble metal, and said particles are coated with an organic film.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein said bonding material having the sheet shape and having the sinterability has a uniform thickness.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein
said substrate comprises an insulating substrate containing SiN or MN, and
said insulating substrate has a surface on said semiconductor element side on which a circuit pattern containing Cu is formed.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein said substrate comprises a conductive substrate containing Cu.

5. The method for manufacturing a semiconductor device according to claim 1 , further comprising (d) cutting out said bonding material from an original bonding material having a sheet shape and having sinterability before said (a), said bonding material having the same size as that of a surface to be subjected to bonding of said semiconductor element,
wherein said bonding material cut out in said (d) is disposed on said substrate in said (a).

6. A method for manufacturing a semiconductor device, comprising:
(a) disposing, on a substrate, a bonding material having a sheet shape and having sinterability;
(b) disposing a semiconductor element on said bonding material after said (a);
(c) sintering said bonding material while applying pressure to said bonding material between said substrate and said semiconductor element; and
(d) cutting out said bonding material from an original bonding material having a sheet shape and having sinterability before said (a), said bonding material having the same size as that of a surface to be subjected to bonding of said semiconductor element,
wherein said bonding material includes particles of Ag or Cu, and said particles are coated with an organic film

wherein said bonding material cut out in said (d) is disposed on said substrate in said (a), said bonding material is cut out with an adsorptive collet in said (d), and said bonding material cut out with said adsorptive collet is carried and disposed in said (a), and
said bonding material cut out with said adsorptive collet in said (d) has the same area as that of the surface to be subjected to bonding of said semiconductor element.

7. The method for manufacturing a semiconductor device according to claim 1 , wherein said bonding material has cushioning properties and tackiness.

Assignees

• Mitsubishi Electric Corp

Inventors

• Hino Yasunari
• Kawabata Daisuke

Classifications

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07353

  changes in shapes · CPC title