Nanowires coated on traces in electronic devices

Patent metadata

Field	Value
Publication number	US-9627320-B2
Application number	US-201113976008-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed.

First claim

What is claimed:

1. An electronic device comprising:
a substrate,
a first electrically conductive region on the substrate, the first electrically conductive region comprising a trace including a metal layer;
a plurality of nanowires positioned on the trace, the plurality of nanowires each including a first end in direct contact with the metal layer and a second end that is electrically isolated from any additional electrically conductive regions comprising a trace on the substrate;
a first dielectric layer positioned in direct contact with the plurality of nanowires;
an additional trace comprising a metal layer positioned on the first dielectric layer, and a plurality of additional nanowires positioned on the additional trace, wherein the first dielectric layer is positioned between the additional trace and the plurality of nanowires, and wherein the first dielectric layer is positioned between the additional trace and the substrate; and
a second dielectric layer positioned on the plurality of additional nanowires, wherein the
second dielectric layer is separated from the substrate by at least the first dielectric layer.

2. The electronic device of claim 1 , the trace including a top surface and first and second side surfaces, wherein the plurality of nanowires are positioned on the top surface and on the first and second side surfaces of the trace.

3. The electronic device of claim 2 , wherein the plurality of nanowires extend outward from the top surface and from the first and second side surfaces in a substantially perpendicular manner.

4. The electronic device of claim 1 , wherein the first dielectric layer comprises an organic polymer material with fillers.

5. The electronic device of claim 1 , wherein the plurality of nanowires comprise zinc oxide.

6. The electronic device of claim 1 , wherein the substrate comprises a semiconductor material and a substrate dielectric layer on the semiconductor material, wherein the trace is positioned on the substrate dielectric layer.

7. The electronic device of claim 1 , wherein the plurality of nanowires each have a length of no greater than 1 μm and a diameter in the range of 10-50 nm.

8. The electronic device of claim 1 , wherein the first dielectric layer is positioned so that the second end of each of the plurality of nanowires is electrically isolated from the additional trace on the substrate.

9. A method for forming an electronic device, comprising:
providing a substrate;
providing an electrically conductive region comprising a first trace on the substrate, the first trace comprising a metal layer;
growing a plurality of nanowires on the first trace, the nanowires each including a first end in direct contact with the metal layer and a second end spaced apart from the first end; and
positioning a first dielectric layer on the plurality of nanowires on the first trace so that the second end is electrically isolated from any additional electrically conductive regions comprising a trace by the first dielectric layer;
providing a second trace comprising a metal layer on the first dielectric layer, wherein the first dielectric layer is positioned between the second trace and the plurality of nanowires on the first trace;
growing an additional plurality of nanowires in direct contact with the metal layer of the second trace; and
providing a second dielectric layer on the additional plurality of nanowires on the second trace, wherein the second dielectric layer is separated from the substrate by at least the first dielectric layer.

10. The method of claim 9 , comprising positioning the first dielectric layer to form a mechanically interlocked structure with at least some of the plurality of nanowires.

11. The method of claim 9 , the trace including a top surface and first and second side surfaces, wherein the plurality of nanowires are positioned on the top surface and on the first and second side surfaces of the trace.

12. The method of claim 9 , further comprising forming the plurality of nanowires to comprise zinc oxide.

13. An electronic device comprising:
a substrate;
a first electrically conductive region on the substrate, the first electrically conductive region comprising a trace comprising a metal layer;
a first layer of nanowires positioned on the trace and including a first end surface positioned on the trace and a second end surface opposite the first end surface;
a first dielectric layer positioned on the first layer of nanowires positioned on the trace, wherein the first dielectric layer is positioned to electrically isolate the first layer of nanowires from any additional electrically conductive regions comprising a trace on the substrate;
a second electrically conductive region on the first dielectric layer, the second electrically conductive region comprising a trace comprising a metal layer; the first dielectric layer positioned between the second electrically conductive region and the first layer of nanowires;
a second layer of nanowires positioned on the metal layer of the second electrically conductive region; and
a second dielectric layer positioned on the second layer of nanowires, wherein the second dielectric layer is separated from the substrate by at least the first dielectric layer.

14. The electronic device of claim 13 , wherein the metal layer of the first electrically conductive region on the substrate includes a top surface and first and second side surfaces, wherein the first layer of nanowires is positioned in direct contact with the top surface and the first and second side surfaces of the metal layer of the first electrically conductive region.

15. The electronic device of claim 13 , wherein the first layer of nanowires and the second layer of nanowires comprise zinc oxide.

16. The electronic device of claim 13 , wherein the first layer of nanowires each have a length of no greater than 1 μm and a diameter in the range of 10-50 nm.

Assignees

• Panat Rahul
• Jaiswal Bhanu
• Intel Corp

Inventors

• Panat Rahul
• Jaiswal Bhanu

Classifications

• H10P14/3426

  Oxides · CPC title

• H10P14/3242

  Structure · CPC title

• H10P14/3241

  being conductive materials · CPC title

• H10P14/265

  using solutions · CPC title

• H10P14/3462

  Nanowires · CPC title