On-chip capacitors and methods of assembling same

Patent metadata

Field	Value
Publication number	US-9627312-B2
Application number	US-201113995525-A
Country	US
Kind code	B2
Filing date	Oct 1, 2011
Priority date	Oct 1, 2011
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.

First claim

What is claimed is:

1. An on-chip capacitor, comprising:
a semiconductive substrate including an active surface and a backside surface;
a back-end metallization disposed upon the active surface;
a passivation structure disposed upon the back-end metallization, wherein the passivation structure includes:
at least first, second, and third electrodes that are parallel planar;
capacitor first and second dielectric layers between the first and third electrodes;
fourth and fifth electrodes;
a first via; and
a second via;

wherein (a) the capacitor first dielectric layer and the capacitor second dielectric layer have the same qualitative chemistries, (b) the first via contacts and penetrates the first electrode and the second via contacts and penetrates the third electrode, (c) the fourth electrode is coplanar with the first electrode and is contacted by the second via, (d) the second electrode is a floater, (e) the fifth electrode is coplanar with the third electrode and contacted by the first via, and (f) the second electrode is above the first electrode and below the third electrode.

2. The on-chip capacitor of claim 1 , wherein the first and fifth electrodes are spaced apart by the second electrode.

3. The on-chip capacitor of claim 1 , wherein the third and the fourth electrodes are spaced apart by the second electrode.

4. The on-chip capacitor of claim 1 , wherein the second via penetrates the fourth electrode.

5. The on-chip capacitor of claim 1 , wherein the first via penetrates the fifth electrode.

6. The on-chip capacitor of claim 5 , wherein the second via penetrates the fourth electrode.

7. The on-chip capacitor of claim 1 , wherein the first via is a power via and the second via is a ground via.

Assignees

• Childs Michael A
• Fischer Kevin J
• Natarajan Sanjay S
• Intel Corp

Inventors

• Childs Michael A
• Fischer Kevin J
• Natarajan Sanjay S

Classifications

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/251

  Materials · CPC title

• H10W72/221

  Structures or relative sizes · CPC title