Semiconductor device with self-aligned interconnects

Patent metadata

Field	Value
Publication number	US-9627310-B2
Application number	US-201213444648-A
Country	US
Kind code	B2
Filing date	Apr 11, 2012
Priority date	Apr 11, 2012
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.

First claim

What is claimed is:

1. A multilayer device comprising:
a substrate;
a first interlayer dielectric (ILD) layer disposed over the substrate, the first ILD layer in direct contact with the substrate;
a first conductive layer including a first plurality of parallel conductive lines each having a first thickness, disposed within the first ILD layer, and extending a partial thickness through the first ILD layer, the first plurality of conductive lines comprising a first conductive line, a second line, and a third conductive line positioned between the first conductive line and the second conductive line, there being no conductive features between the first conductive line and the second conductive line except the third conductive line,
wherein the first plurality of conductive lines has an orientation in a first direction,
wherein at least a portion of the first ILD layer is between the first conductive layer and the substrate;
a second ILD layer having a second thickness disposed over the first ILD layer; and
a second conductive layer including a second plurality of conductive lines each having a third thickness, disposed within the second ILD layer,
wherein the first, second, and third thicknesses are substantially equal,
wherein the first plurality of conductive lines are formed of a first metal and the second plurality of conductive lines are formed of a second metal that is different than the first metal,
wherein at least one conductive line of the second plurality of conductive lines has an orientation in a second direction and is formed adjacent to and in direct contact with the third conductive line, the at least one conductive line of the second plurality of conductive lines having a first end positioned between the first conductive line and the third conductive line and a second end positioned between the third conductive line and the second conductive line, wherein the second direction is orthogonal to the first direction,
wherein the at least one conductive line of the second plurality of conductive lines contacts the third conductive line of the first plurality of conductive lines at an interface, and
wherein the interface provides electrical contact between the at least one conductive line of the second plurality of conductive lines and the third conductive line of the first plurality of conductive lines without the use of a via,
wherein the interface spans a width of the third conductive line of the first plurality of conductive lines, the width extending from a first sidewall of the third conductive line of the first plurality of conductive lines to a second sidewall of the third conductive line of the first plurality of conductive lines.

2. The multilayer device of claim 1 wherein the at least one conductive line of the second plurality of conductive lines extends through the second ILD layer.

3. The multilayer device of claim 1 wherein the first ILD layer includes a material selected from the group consisting of silicon nitride, silicon oxide, and silicon oxynitride.

4. The multilayer device of claim 3 wherein the second ILD layer includes a material selected from the group consisting of silicon nitride, silicon oxide, and silicon oxynitride.

5. The multilayer device of claim 1 wherein the first and second plurality of conductive lines include a material selected from the group consisting of aluminum (Al), tungsten (W), and copper (Cu).

6. The multilayer device of claim 1 wherein the first ILD layer and the second ILD layer are low-k dielectric layers.

7. A device comprising:
a substrate;
a first interlayer dielectric (ILD) layer disposed over the substrate, the first ILD layer in direct contact with the substrate;
a first conductive layer having a first thickness, disposed within the first ILD layer, the first conductive layer including a first plurality of conductive lines having the first thickness and an orientation in a first direction, and extending a partial thickness through the first ILD layer, the first plurality of conductive lines comprising a first conductive line, a second line, and a third conductive line positioned between the first conductive line and the second conductive line, there being no conductive features between the first conductive line and the second conductive line except the third conductive line,
wherein part of the first ILD layer is between the first conductive layer and the substrate;
a second ILD layer having a second thickness, disposed over the first ILD layer and over the first plurality of conductive lines; and
a second conductive layer having a third thickness, disposed within the second ILD layer and over the first ILD layer and over the first plurality of conductive lines, the second conductive layer including at least one conductive line of a second plurality of conductive lines having the third thickness and an orientation in a second direction, the at least one conductive line of the second plurality of conductive lines having a first end positioned between the first conductive line and the third conductive line and a second end positioned between the third conductive line and the second conductive line,
wherein the first, second, and third thicknesses are substantially equal,
wherein the first plurality of conductive lines are formed of a metal and the second plurality of conductive lines are formed of polysilicon,
wherein the second direction is perpendicular to the first direction,
wherein the at least one conductive line of the second plurality of conductive line traverses the third conductive line of the first plurality of conductive lines at an interface spanning a width of the conductive line of the first plurality of conductive lines, the width extending from a first sidewall of the third conductive line of the first plurality of conductive lines to a second sidewall of the third conductive line of the first plurality of conductive lines,
wherein a surface of the third conductive line of the first plurality of conductive lines is in electrical contact with a surface of the at least one conductive line of the second plurality of conductive lines at the interface, and
wherein the interface is a self-aligned interconnect.

8. The device of claim 7 wherein the second conductive layer includes a top surface that is substantially coplanar with a top surface of the second ILD layer, and
wherein the second conductive layer includes a bottom surface that is substantially coplanar with a bottom surface of the second ILD layer.

9. A multilayer device comprising:
a substrate;
a first conductive layer having a first thickness, including a first plurality of conductive lines having the first thickness, surrounded by a first interlayer dielectric (ILD) layer, and extending a partial thickness through the first ILD layer, the first plurality of conductive lines comprising a first conductive line, a second line, and a third conductive line positioned between the first conductive line and the second conductive line, there being no conductive features between the first conductive line and the second conductive line except the third conductive line,
wherein the first ILD layer is directly coupled to the substrate,
wherein the first plurality of conductive lines are not in direct contact with the substrate;
a second ILD layer having a second thickness, disposed over the first ILD layer; and
a second conductive layer having a third thickness, including a second plurality of conductive lines having the third thickness, disposed within the second ILD layer,
wherein the first, second, and third thicknesses are substantially equal,
wherein the first plurality of conductive lines are formed of a first metal and the second plurality of conductive lines are forme

Assignees

• Chang Shih-Ming
• Hsieh Ken-Hsien
• Ou Tsong-Hua
• Liu Ru-Gun
• Fan Fang-Yu
• Hou Yuan-Te
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Shih-Ming
• Hsieh Ken-Hsien
• Ou Tsong-Hua
• Liu Ru-Gun
• Fan Fang-Yu
• Hou Yuan-Te

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title