Methods of forming semiconductor device having gate electrode

Patent metadata

Field	Value
Publication number	US-9627207-B2
Application number	US-201514736320-A
Country	US
Kind code	B2
Filing date	Jun 11, 2015
Priority date	Nov 7, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Methods of forming a semiconductor device are provided. An active region is formed on a substrate. A temporary gate crossing the active region and a capping pattern covering the temporary gate are formed. Spacers are formed on sidewalls of the temporary gate. A growth-blocking layer is locally formed in an upper edge of the temporary gate. A source/drain region is formed on the active region adjacent to the temporary gate. The capping pattern, the first growth-blocking layer, and the temporary gate are removed to expose the active region. A gate electrode is formed on the exposed active region.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming an active region on a substrate;
forming a temporary gate crossing the active region and a capping pattern on the temporary gate;
forming spacers on sidewalls of the temporary gate;
forming a first growth-blocking layer selectively in a portion of the temporary gate that is adjacent an edge of an upper surface of the temporary gate after forming the spacers;
forming a source/drain region on the active region adjacent to the temporary gate;
removing the capping pattern, the first growth-blocking layer, and the temporary gate to expose the active region; and
forming a gate electrode on the exposed active region.

2. The method of claim 1 , wherein the forming of the first growth-blocking layer includes implanting dopants into the temporary gate,
the temporary gate includes polysilicon, and
the dopants include As, N, C, O, or a combination thereof.

3. The method of claim 1 , wherein the forming of the first growth-blocking layer includes a tilted ion-implantation process, and
the tilted ion-implantation process is performed by implanting dopants into the temporary gate at an angle which includes a horizontal angle in a range of 80 to 89 degrees, 91 to 100 degrees, 260 to 269 degrees, 271 to 280 degrees, or a combination thereof with respect to a horizontal major axis of the temporary gate, and a vertical angle in a range of 30 to 89 degrees with respect to a line perpendicular to a surface of the substrate.

4. The method of claim 1 , wherein the forming of the first growth-blocking layer comprises:
partially removing the active region after forming the spacers and forming a recessed region; and
implanting dopants into the temporary gate using a tilted ion-implantation process.

5. The method of claim 1 , further comprising forming a second growth-blocking layer in an upper portion of the temporary gate.

6. The method of claim 5 , wherein the first growth-blocking layer is in contact with a sidewall of the second growth-blocking layer.

7. The method of claim 5 , wherein the first growth-blocking layer surrounds sidewalls of the second growth-blocking layer.

8. The method of claim 5 , wherein a lower end of the first growth-blocking layer is disposed at a lower level than a lower end of the second growth-blocking layer.

9. The method of claim 5 , wherein the forming of the second growth-blocking layer comprises:
forming a temporary gate layer on the active region;
forming the second growth-blocking layer in the upper portion of the temporary gate layer using an ion-implantation process;
forming a capping pattern on the second growth-blocking layer; and
patterning the temporary gate layer to form the temporary gate,
wherein the second growth-blocking layer remains between the capping pattern and the temporary gate after forming the temporary gate.

10. The method of claim 5 , wherein the temporary gate includes polysilicon,
the second growth-blocking layer includes dopants implanted into the polysilicon, and
the dopants include As, N, C, O, or a combination thereof.

11. The method of claim 1 , wherein the forming of the source/drain region comprises:
partially removing the active region to form a recessed region before forming the first growth-blocking layer; and
forming the source/drain region in the recessed region after forming the first growth-blocking layer.

12. The method of claim 1 , wherein the source/drain region is formed after forming the first growth-blocking layer using an epitaxial growth process.

13. A method of forming a semiconductor device, comprising:
defining a fin active region on a substrate;
forming a temporary gate layer on the fin active region;
forming a first growth-blocking layer in an uppermost portion of the temporary gate layer by implanting dopants into the uppermost portion of the temporary gate layer, the dopants including As, N, C, O, or combination thereof;
forming a capping layer on the first growth-blocking layer;
forming a temporary gate structure by sequentially the capping layer, the first growth-blocking layer and the temporary gate layer;
forming spacers on sidewalls of the temporary gate structure;
forming source/drain regions on the fin active region adjacent to sidewalls of the temporary gate structure;
removing the temporary gate structure to expose the fin active region; and
forming a gate electrode on the exposed fin active region.

14. The method of claim 13 , further comprising forming a second growth-blocking layer in a portion of the first growth-blocking layer adjacent a side of the first growth-blocking layer.

15. The method of claim 14 , wherein the second growth-blocking layer is formed in an upper corner of the temporary gate layer.

16. The method of claim 14 , wherein the second growth-blocking layer is formed after forming the spacers and before forming source/drain regions,
wherein the dopants comprises first dopants, and
wherein forming the second growth-blocking layer comprises performing a tilted ion-implantation process to implant second dopants into the portion of the first growth-blocking layer adjacent the side of the first growth-blocking layer, and the second dopants include As, N, C, O, or a combination thereof.

17. The method of claim 13 , wherein the source/drain regions are formed using an epitaxial growth process after forming the spacers.

18. The method of claim 17 , further comprising partially removing portions of the fin active region to form recesses in the fin active region adjacent the respective sidewalls of the temporary gate structure after forming the spacers, wherein the source/drain regions are formed in the respective recesses.

19. The method of claim 13 , wherein forming the first growth-blocking layer comprises implanting the dopants at a dose of about 1E13 atoms/cm 2 to about 1E16 atoms/cm 2 .

20. A method of forming a semiconductor device, comprising:
defining a fin active region on a substrate;
forming a temporary gate layer covering an upper surface and sidewalls of the fin active region;
forming a first growth-blocking layer in an upper portion of the temporary gate layer;
forming a capping pattern on the first growth-blocking layer;
patterning the temporary gate layer and forming a temporary gate, wherein the first growth-blocking layer remains between the capping pattern and the temporary gate;
forming spacers on sidewalls of the temporary gate and the first growth-blocking layer;
forming a recessed region by partially removing the fin active region;
forming a second growth-blocking layer in a portion of the temporary gate that is adjacent an edge of an upper surface of the temporary gate and a portion the first growth-blocking layer that is adjacent a side of the first growth-blocking layer;
forming a source/drain region in the recessed region;
removing the capping pattern, the first growth-blocking layer, the second growth-blocking layer, and the temporary gate to expose the fin active region; and
forming a gate electrode on the exposed fin active region.

Assignees

• Jang Sunguk
• Kim Juyeon
• Son Hosung
• Shin Dongsuk
• Lee Jeongmin
• Samsung Electronics Co Ltd

Inventors

• Jang Sunguk
• Kim Juyeon
• Son Hosung
• Shin Dongsuk
• Lee Jeongmin

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171 Primary

  being group IV material · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic