Method for manufacturing thin film semiconductor device

Patent metadata

Field	Value
Publication number	US-9627198-B2
Application number	US-89479110-A
Country	US
Kind code	B2
Filing date	Sep 30, 2010
Priority date	Oct 5, 2009
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H 2 O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.

First claim

The invention claimed is:

1. A manufacturing method of a semiconductor device comprising steps of:
forming a gate electrode layer over a substrate,
forming a gate insulating layer over the gate electrode layer;
introducing the substrate into a first treatment chamber;
performing a first sputtering operation using an oxide semiconductor target to form an oxide semiconductor layer over the gate insulating layer;
heating the substrate, the gate insulating layer, and the oxide semiconductor layer at a temperature higher than or equal to 100° C. and lower than or equal to 400° C. after performing the first sputtering operation; and
forming, over and in contact with the oxide semiconductor layer, a silicon oxide layer including defects at a temperature higher than or equal to 0° C. and lower than or equal to 50° C. after the step of heating the substrate the gate insulating layer, and the oxide semiconductor layer,
wherein the substrate is heated during the step of forming of the oxide semiconductor layer at a first temperature.

2. The manufacturing method of a semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes at least one of indium, gallium, and zinc.

3. The manufacturing method of a semiconductor device according to claim 1 ,
wherein a mixed region having a thickness comprised between 1 nm and 10 nm is provided at an interface between the oxide semiconductor layer and the silicon oxide layer,
wherein the mixed region includes oxygen, silicon, and at least one kind of metal element included in the oxide semiconductor layer.

4. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the silicon oxide layer is formed by performing a second sputtering operation.

5. The manufacturing method of a semiconductor device according to claim 1 , wherein a filling rate of the oxide semiconductor target is greater than or equal to 90%.

6. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the step of heating the substrate, the gate insulating layer, and the oxide semiconductor layer is performed in a second chamber, and
wherein the step of forming the silicon oxide layer is performed in a third chamber.

7. The manufacturing method of a semiconductor device according to claim 1 , wherein the silicon oxide layer is in contact with the gate insulating layer.

8. A manufacturing method of a semiconductor device comprising steps of:
forming a gate electrode layer over a substrate,
forming a gate insulating layer over the gate electrode layer;
introducing the substrate into a first treatment chamber;
introducing into the first treatment chamber an oxygen gas and a rare gas, wherein each of the oxygen gas and the rare gas has a purity of 7N or higher;
performing a first sputtering operation using an oxide semiconductor target to form an oxide semiconductor layer having hydrogen concentration of 2×10 19 cm −3 or less when measured by secondary ion mass spectrometry, over the gate insulating layer;
heating the substrate, the gate insulating layer, and the oxide semiconductor layer at a temperature higher than or equal to 100° C. and lower than or equal to 400° C. after performing the first sputtering operation; and
then forming, over the oxide semiconductor layer, a silicon oxide layer including defects at a temperature higher than or equal to 0° C. and lower than or equal to 50° C.,
wherein the substrate is heated during the step of forming of the oxide semiconductor layer at a first temperature.

9. The manufacturing method of a semiconductor device according to claim 8 , wherein the oxide semiconductor layer includes at least one of indium, gallium, and zinc.

10. The manufacturing method of a semiconductor device according to claim 8 ,
wherein a mixed region having a thickness comprised between 1 nm and 10 nm is provided at an interface between the oxide semiconductor layer and the silicon oxide layer,
wherein the mixed region includes oxygen, silicon, and at least one kind of metal element included in the oxide semiconductor layer.

11. The manufacturing method of a semiconductor device according to claim 8 ,
wherein the silicon oxide layer is formed by performing a second sputtering operation.

12. The manufacturing method of a semiconductor device according to claim 8 , wherein a filling rate of the oxide semiconductor target is greater than or equal to 90%.

13. The manufacturing method of a semiconductor device according to claim 8 ,
wherein the step of heating the substrate, the gate insulating layer, and the oxide semiconductor layer is performed in a second chamber, and
wherein the step of forming the silicon oxide layer is performed in a third chamber.

14. The manufacturing method of a semiconductor device according to claim 8 , wherein the silicon oxide layer is in contact with the gate insulating layer.

Assignees

• Yamazaki Shunpei
• Miyanaga Akiharu
• Takahashi Masahiro
• Kishida Hideyuki
• Sakata Junichiro
• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Miyanaga Akiharu
• Takahashi Masahiro
• Kishida Hideyuki
• Sakata Junichiro

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6938

  the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title