Memory device having page state informing function

Patent metadata

Field	Value
Publication number	US-9627015-B2
Application number	US-201514852890-A
Country	US
Kind code	B2
Filing date	Sep 14, 2015
Priority date	Nov 24, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A memory device, system, and/or method are provided for performing a page state informing function. The memory device may compare one or more row addresses received along with a command, determine the page open/close state according to a page hit or miss generated as a result of comparison, count read or write commands with respect to pages corresponding to a same row address, and determine the page open/close state according to a read or write command number generated as a result of counting. The memory device may determine a page open/close state with respect to a corresponding page based on a page hit/miss and a read or write command number and output a flag signal. The memory device may provide the page open/close state for each channel. A memory controller may establish different page open/close policies for each channel.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array comprising a plurality of pages addressed by row address; and
a control logic unit configured to
determine whether at least one page among the plurality of pages is in an open state or a closed state, based on a command and the row address of the at least one page, the determination includes,
generating results based on at least two row addresses received along with the command,
generating a page hit or a page miss based on the results, and
determining, according to the page hit or the page miss, whether each of the plurality of pages is in the open state or the closed state, and

output a flag signal indicating whether the at least one page is in the open state or the closed state.

2. The memory device of claim 1 , wherein the control logic unit is configured to
count read or write commands with respect to a page corresponding to a row address; and
determine, according to a read or write command number generated based on the counting, whether each of the plurality of pages is in the open state or the closed state.

3. The memory device of claim 1 , wherein the control logic unit comprises:
a register configured to store one or more row addresses received along with a command;
a comparator configured to generate results based on at least two of the row addresses stored in the register and generate a page hit or a page miss;
a counter configured to count read or write commands with respect to a page corresponding to a row address and generate a read or write command number; and
a logic circuit unit configured to determine, based on the page hit or page miss and the read or write command number, whether each of the plurality of pages is in the open state or the closed state.

4. The memory device of claim 1 , wherein,
the memory cell array is configured as one or more banks comprising the plurality of pages;
the control logic unit further comprises a hit profiler corresponding to each of the one or more banks; and
each hit profiler is configured to determine whether each of the plurality of pages of a bank corresponding to said hit profiler is in the open state or the closed state.

5. The memory device of claim 4 , wherein each hit profiler comprises:
a register configured to store one or more row addresses received along with a command associated with the bank corresponding to said hit profiler;
a comparator configured to generate results based on the one or more row addresses stored in the register and generate a page hit or a page miss;
a counter configured to count read or write commands with respect to a page corresponding to a same row address associated with the corresponding bank and generate a read or write command number; and
the control logic unit further comprises a logic circuit unit configured to determine whether the page corresponding to the same row address associated with the corresponding bank are in the open state or the closed state, based on the page hit or the page miss and the generated read or write command number.

6. The memory device of claim 1 , wherein the page open state or the closed state is stored in a multipurpose register (MPR) of a mode register of the memory device.

7. The memory device of claim 6 , wherein the flag signal is output according to a mode register read command.

8. A method of operating a memory device comprising a plurality of pages addressed by row addresses, the method comprising:
receiving a command and the row addresses;
determining a page open/close state with respect to the plurality of pages based on the command and the row addresses, the determining including,
generating results based on two or more row addresses received along with the command,
generating a page hit or miss based on the results, and
determining the page open/close state according to the page hit or miss; and

outputting a flag signal, the flag signal indicating the page open/close state.

9. The method of claim 8 , wherein the number of the row addresses to be compared is determined according to a desired precision of the generating the page hit or page miss.

10. The method of claim 8 , wherein the determining of the page open/closed state comprises:
counting read or write commands with respect to pages corresponding to a row address; and
determining the page open/close state according to a read or write command number generated as a result of the counting.

11. The method of claim 8 , wherein the memory comprises one or more banks comprising the plurality of pages, the method further comprising:
determining the page open/close state with respect to the plurality of pages of a corresponding bank among the one or more banks.

12. The method of claim 11 , wherein the determining of the page open/close state comprises:
generating results based on one or more row addresses received along with a command associated with the corresponding bank; and
determining the page open/close state with respect to the plurality of pages of the corresponding bank according to a page hit or miss generated based on the results.

13. The method of claim 11 , wherein the determining of the page open/close state comprises:
counting read or write commands with respect to the plurality of pages corresponding to a same row address associated with the corresponding bank; and
determining the page open/close state with respect to the plurality of pages of the corresponding bank according to a read or write command number generated as a result of the counting.

14. A system comprising:
at least one processor configured to read or write (R/W) data to a memory address;
at least one memory controller configured to access at least one memory device in accordance to a R/W command from the processor; and
the memory device configured to determine a page state for a page associated with the R/W command, the page state indicating whether the page is in an open or closed stated, the determination including,
generating results based on two or more memory addresses received along with the R/W command,
generating a page hit or miss based on the results, and

determining the page state according to the page hit or miss.

15. The system of claim 14 , wherein the memory device includes:
a control logic configured to,
receive the R/W command from the memory controller, the R/W command including a memory address,
determine the page state by determining whether the memory address corresponds to an open page in the memory device, and
generate a signal indicating the page state.

16. The system of claim 15 , wherein
the received R/W command includes a plurality of memory addresses; and
the control logic is configured to determine the page state by,
counting a number of the plurality of memory addresses that correspond to the open page in the memory device,
determining whether the number is greater than a desired threshold number, and
generating the signal indicating the page state based on the determining.

17. The system of claim 14 , wherein
the memory controller includes a plurality of memory controllers;
the memory device includes a plurality of memory devices; and
the plurality of memory devices are each configured to operate as a memory channel.

18. The system of claim 17 , wherein each of the memory controllers is configured to set a page policy for a respective one of the memory devices.

Assignees

• Sohn Young-Soo
• Park Kwang-Il
• Kim Sei-Jin
• Kim Tae-Young
• Samsung Electronics Co Ltd

Inventors

• Sohn Young-Soo
• Park Kwang-Il
• Kim Sei-Jin
• Kim Tae-Young

Classifications

• G11C7/109 Primary

  Control signal input circuits · CPC title

• G11C2207/2272

  Latency related aspects · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title