GOA circuit, array substrate, display device and driving method

Patent metadata

Field	Value
Publication number	US-9626922-B2
Application number	US-201614993571-A
Country	US
Kind code	B2
Filing date	Jan 12, 2016
Priority date	Jul 18, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

There are provided a GOA circuit, an array substrate, a display device and a driving method. The GOA circuit includes clock signal input lines and more than two GOA units connected in cascade, wherein each of the GOA units includes a selection signal output sub-unit and a selection sub-unit; the selection signal output sub-unit is configured to receive a source signal, and output a selection signal in accordance with the source signal; the selection sub-unit receives the selection signal and N clock signals, and outputs the received signal in accordance with the selection signal; and the clock signal input lines are no less than a number of N, and are configured to input the clock signals to the selection sub-unit, where N is an integer number which is higher than or equal to two. The gate driving structure of the GOA circuit, the array substrate and the display device occupies a small area. The driving method can achieve a single dot polarity inversion.

First claim

What is claimed is:

1. A driving method for a display device comprising a pixel array and a GOA circuit, wherein each row of the pixels is configured to correspond to two gate lines, the pixels located in odd columns are connected to one of the two gate lines, and the pixels located in even columns are connected to the other of the two gate lines, and the pixels on (2i+1) th column and pixels on 2(i+1) th column are configured to share one data line, where i is an integer equal to or larger than zero; the GOA circuit comprises at least two GOA units connected in cascade each being connected to adjacent N gate lines and configured to sequentially turn on the N gate lines connected thereto;
the driving method comprising:
dividing each image frame into N fields for display;
during a period of each field, turning on one gate line by each GOA unit under a control of a corresponding clock signal;
during each field period, maintaining polarities of voltages outputted from all of the data lines identical;
wherein polarities of voltages outputted from data lines during a (4S+1) th field are opposite to those in a (4S+2) th field;
polarities of voltages outputted from data lines during the (4S+2) th field are identical to those in a (4S+3) th field;
polarities of voltages outputted from data lines during the (4S+3) th field are opposite to those in a (4S+4) th field;
wherein, S is an integer equal to or larger than zero, and value of (4S+4) is less than or equal to N; and
N represents the number of clock signals imported to the GOA circuit, and is a multiple of 4.

2. A driving method for a display device comprising a pixel array and GOA circuit, wherein each row of the pixels is connected to one gate line and each column of the pixels is connected to one data line; the GOA circuit comprises at least two GOA units connected in cascade each being connected to adjacent N gate lines and configured to sequentially turn on the N gate lines connected thereto;
the driving method comprising:
dividing each image frame into N fields for display to achieve a single dot polarity inversion;
during a period of each field, turning on one gate line by each GOA unit under a control of a corresponding clock signal;
wherein a period of polarity inversion of a voltage outputted from each of data lines is equal to the period of each field, and polarities of voltages outputted from two adjacent data lines are opposite to each other,
wherein N represents the number of clock signals imported into the GOA circuit.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Huang Jiacheng
• He Jian
• Feng Xia

Classifications

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2320/0673

  for control of gamma adjustment, e.g. selecting another gamma curve · CPC title

• G09G3/3659

  the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes · CPC title

• G09G3/36

  using liquid crystals · CPC title