Page management approach to fully utilize hardware caches for tiled rendering

Patent metadata

Field	Value
Publication number	US-9626735-B2
Application number	US-201314124845-A
Country	US
Kind code	B2
Filing date	Jun 24, 2013
Priority date	Jun 24, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.

First claim

We claim:

1. A system comprising:
a battery to supply power to the system;
a frame buffer to include one or more tiles associated with an image, each of the one or more tiles including a plurality of pages;
a cache;
a host processor; and
at least one computer readable storage medium including a set of instructions which, if executed by the host processor, cause the system to:
identify the one or more tiles associated with the image;
order a linear stream of pages associated with the frame buffer into an entirety of each of the one or more tiles; and
allocate the linear stream of pages to the cache,

wherein each of the pages is an addressable page included in the one or more tiles.

2. The system of claim 1 , wherein the linear stream of pages is to be allocated to the cache in accordance with a fixed set selection policy of the cache.

3. The system of claim 1 , further including a tile renderer, wherein the instructions, if executed, cause the system to:
conduct a first transfer of the one or more tiles from the tile renderer to the cache; and
conduct a second transfer of the one or more tiles from the cache to the frame buffer.

4. The system of claim 3 , wherein the first transfer is to result in full utilization of the cache.

5. The system of claim 3 , wherein a first transfer module is to repeat the first transfer for a plurality of tiles associated with the image and a second transfer module is to repeat the second transfer for the plurality of tiles, the system further including a third transfer module to conduct a third transfer of the plurality of tiles from the frame buffer to a display.

6. The system of claim 1 , wherein the one or more tiles is to include a plurality of color values for the image on a pixel-by-pixel basis.

7. An apparatus comprising:
a frame buffer to include one or more tiles associated with an image, each of the one or more tiles including a plurality of pages;
a processor configured to execute:
a tile module to identify the one or more tiles associated with the image;
a page module to order a linear stream of pages associated with the frame buffer into an entirety of each of the one or more tiles: and
an allocation module to allocate the linear stream of pages to a cache,
wherein each of the pages is an addressable page included in the one or more tiles.

8. The apparatus of claim 7 , wherein the linear stream of pages is to be allocated to the cache in accordance with a fixed set selection policy of the cache.

9. The apparatus of claim 7 , further including:
a first transfer module to conduct a first transfer of the one or more tiles from a tile renderer to the cache; and
a second transfer module to conduct a second transfer of the one or more tiles from the cache to the frame buffer.

10. The apparatus of claim 9 , wherein the first transfer is to result in full utilization of the cache.

11. The apparatus of claim 9 , wherein the first transfer module is to repeat the first transfer for a plurality of tiles associated with the image and the second transfer module is to repeat the second transfer for the plurality of tiles, the apparatus further including a third transfer module to conduct a third transfer of the plurality of tiles from the frame buffer to a display.

12. The apparatus of claim 7 , wherein the one or more tiles is to include a plurality of color values for the image on a pixel-by-pixel basis.

13. A method comprising:
identifying one or more tiles associated with an image, each of the one or more tiles including a plurality of pages;
ordering a linear stream of pages associated with a frame buffer into an entirety of each of the one or more tiles: and
allocating the linear stream of pages to a cache,
wherein each of the pages is an addressable page included in the one or more tiles.

14. The method of claim 13 , wherein the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.

15. The method of claim 13 , further including:
conducting a first transfer of the one or more tiles from a tile renderer to the cache; and
conducting a second transfer of the one or more tiles from the cache to the frame buffer.

16. The method of claim 15 , wherein the first transfer results in full utilization of the cache.

17. The method of claim 15 , further including:
repeating the first transfer and the second transfer for a plurality of tiles associated with the image; and
conducting a third transfer of the plurality of tiles from the frame buffer to a display.

18. The method of claim 15 , wherein the one or more tiles include a plurality of color values for the image on a pixel-by-pixel basis.

19. At least one non-transitory computer readable storage medium comprising a set of instructions which, if executed by a computing device, cause the computing device to:
identify one or more tiles associated with an image, each of the one or more tiles including a plurality of pages;
order a linear stream of pages associated with a frame buffer into an entirety of each of the one or more tiles: and
allocate the linear stream of pages to a cache,
wherein each of the pages is an addressable page included in the one or more tiles.

20. The at least one computer readable storage medium of claim 19 , wherein the linear stream of pages is to be allocated to the cache in accordance with a fixed set selection policy of the cache.

21. The at least one computer readable storage medium of claim 19 , wherein the instructions, if executed, cause a computing device to:
conduct a first transfer of the one or more tiles from a tile renderer to the cache; and
conduct a second transfer of the one or more tiles from the cache to the frame buffer.

22. The at least one computer readable storage medium of claim 21 , wherein the first transfer is to result in full utilization of the cache.

23. The at least one computer readable storage medium of claim 21 , wherein the instructions, if executed, cause a computing device to:
repeat the first transfer and the second transfer for a plurality of tiles associated with the image; and
conduct a third transfer of the plurality of tiles from the frame buffer to a display.

24. The at least one computer readable storage medium of claim 19 , wherein the one or more tiles is to include a plurality of color values for the image on a pixel-by-pixel basis.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Navale Aditya

Classifications

• G06F2212/455

  Image or video data · CPC title

• G09G2360/121

  using a cache memory · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G09G2360/122

  Tiling · CPC title

• G09G5/363

  Graphics controllers · CPC title