Input/output acceleration in virtualized information handling systems

Patent metadata

Field	Value
Publication number	US-9626324-B2
Application number	US-201414326122-A
Country	US
Kind code	B2
Filing date	Jul 8, 2014
Priority date	Jul 8, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Methods and systems for I/O acceleration on a virtualized information handling system include loading a storage virtual appliance as a virtual machine on a hypervisor. The hypervisor may execute using a first processor and a second processor. The storage virtual appliance is accessed by the hypervisor using a PCI-E device driver that is mapped to a first PCI-E NTB logical endpoint at the first processor. A second PCI-E device driver may be loaded on the storage virtual appliance that accesses the hypervisor and is mapped to a second PCI-E NTB logical endpoint at the second processor. A data transfer operation may be executed between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint. The data transfer operation may be a read or a write operation.

First claim

What is claimed is:

1. A method executed using at least two processors, including a first processor and a second processor, the method comprising:
loading a storage virtual appliance as a virtual machine on a hypervisor executing using the first processor and the second processor, wherein the storage virtual appliance is accessed by the hypervisor using a second Peripheral Component Interconnect Express (PCI-E) device driver that is mapped to a PCI-E non-transparent bridge (NTB) at a second PCI-E NTB logical endpoint at the second processor;
loading a first PCI-E device driver on the storage virtual appliance that accesses the hypervisor and is mapped to the PCI-E NTB at a first PCI-E NTB logical endpoint at the first processor;
loading a first storage driver on the storage virtual appliance that accesses a first central processing unit (CPU) direct memory access (DMA) of the first processor for a first DMA data transfer operation of a plurality of first CPU DMA data transfer operations; and
executing the first DMA data transfer operation between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint,
wherein the hypervisor executes in the second memory space,
wherein the storage virtual appliance executes in the first memory space, and
wherein the PCI-E NTB provides address translation between the first memory space and the second memory space.

2. The method of claim 1 , wherein the first DMA data transfer operation is initiated from one of: the first memory space and the second memory space.

3. The method of claim 1 , further comprising:
loading a second storage driver on the hypervisor that accesses a second central processing unit (CPU) direct memory access (DMA) of the second processor for a second DMA data transfer operation of a plurality of second CPU DMA data transfer operations; and
executing the second DMA data transfer operation between the first memory space and the second memory space.

4. The method of claim 3 , wherein the first DMA data transfer operation occurs from the first memory space to the second memory space.

5. The method of claim 3 , wherein the first DMA data transfer operation occurs from the second memory space to the first memory space.

6. The method of claim 1 , wherein the first DMA data transfer operation includes a programmed input/output (PIO).

7. The method of claim 1 , wherein the first processor is associated with a first physical memory bank and the second processor is associated with a second physical memory bank;
wherein loading the storage virtual appliance includes specifying the first processor for the first CPU DMA data transfer operations; and
wherein the first PCI-E NTB logical endpoint is exclusively mapped to the first physical memory bank.

8. An article of manufacture comprising a non-transitory computer-readable medium storing instructions, that, when executed by at least two processors, including a first processor and a second processor, cause the two processors to:
load a storage virtual appliance as a virtual machine on a hypervisor executing using the first processor and the second processor, wherein the storage virtual appliance is accessed by the hypervisor using a second Peripheral Component Interconnect Express (PCI-E) device driver that is mapped to a PCI-E non-transparent bridge (NTB) at a second PCI-E NTB logical endpoint at the second processor;
load a first PCI-E device driver on the storage virtual appliance that accesses the hypervisor and is mapped to the PCI-E NTB at a first PCI-E NTB logical endpoint at the first processor;
load a first storage driver on the storage virtual appliance that accesses a first central processing unit (CPU) direct memory access (DMA) of the first processor for a first DMA data transfer operation of a plurality of first CPU DMA data transfer operations; and
execute the first DMA data transfer operation between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint,
wherein the hypervisor executes in the second memory space,
wherein the storage virtual appliance executes in the first memory space, and
wherein the PCI-E NTB provides address translation between the first memory space and the second memory space.

9. The article of manufacture of claim 8 , wherein the first DMA data transfer operation is initiated from one of: the first memory space and the second memory space.

10. The article of manufacture of claim 8 , further comprising:
load a second storage driver on the hypervisor that accesses a second central processing unit (CPU) direct memory access (DMA) of the second processor for a second DMA data transfer operation of a plurality of second CPU DMA data transfer operations; and
execute the second DMA data transfer operation between the first memory space and the second memory space.

11. The article of manufacture of claim 10 , wherein the first DMA data transfer operation occurs from the first memory space to the second memory space.

12. The article of manufacture of claim 10 , wherein the first DMA data transfer operation occurs from the second memory space to the first memory space.

13. The article of manufacture of claim 8 , wherein the first DMA data transfer operation includes a programmed input/output (PIO).

14. The article of manufacture of claim 8 , wherein the first processor is associated with a first physical memory bank and the second processor is associated with a second physical memory bank;
wherein loading the storage virtual appliance includes specifying the first processor for the first CPU DMA data transfer operations; and
wherein the first PCI-E NTB logical endpoint is exclusively mapped to the first physical memory bank.

15. An information handling system comprising:
a processor subsystem having access to a memory subsystem, the processor subsystem including a first processor and a second processor, wherein the memory subsystem stores instructions executable by the processor subsystem, that, when executed by the processor subsystem, cause the processor subsystem to:
load a storage virtual appliance as a virtual machine on a hypervisor executing using the first processor and the second processor, wherein the storage virtual appliance is accessed by the hypervisor using a second Peripheral Component Interconnect Express (PCI-E) device driver that is mapped to a PCI-E non-transparent bridge (NTB) at a second PCI-E NTB logical endpoint at the first second processor;
load a first PCI-E device driver on the storage virtual appliance that accesses the hypervisor and is mapped to the PCI-E NTB at a first PCI-E NTB logical endpoint at the first processor;
load a first storage driver on the storage virtual appliance that accesses a first central processing unit (CPU) direct memory access (DMA) of the first processor for a first DMA data transfer operation of a plurality of first CPU DMA data transfer operations; and
execute the first DMA data transfer operation between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint,
wherein the hypervisor executes in the second memory space,
wherein the storage virtual appliance executes in the first memory space, and
wherein the PCI-E NTB provides address translation between the first memory space and the second memory space.

16. The information handling system of claim 15 , wherein the first DMA data tr

Assignees

• Chawla Gaurav
• Hormuth Robert Wayne
• Molloy Michael Karl
• Iyer Shyam T
• Dell Products Lp

Inventors

• Chawla Gaurav
• Hormuth Robert Wayne
• Molloy Michael Karl
• Iyer Shyam T

Classifications

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title