Allocating lanes in a peripheral component interconnect express (‘PCIe’) bus

Patent metadata

Field	Value
Publication number	US-9626319-B2
Application number	US-201313974519-A
Country	US
Kind code	B2
Filing date	Aug 23, 2013
Priority date	Aug 23, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device.

First claim

What is claimed is:

1. An apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
determining performance capabilities of a device coupled to a Peripheral Component Interconnect Connect Interface Express (PCIe) bus, including:
retrieving, from a downstream device, performance capabilities of a downstream device by initiating performance tests with the downstream device, wherein the performance tests include ping operations directed to the downstream device that determine a response time of the downstream device;
maintaining a repository that associates various device types with performance capabilities of each of the various device types;
determining a device type for the device coupled to the PCIe bus;
retrieving, from the repository, performance capabilities of the device; and
determining whether one or more performance capabilities of a downstream device are less than the performance capabilities of the device coupled to the PCIe bus, wherein the downstream device is coupled to the device over a data communications channel other than the PCIe bus; and

allocating, in response to determining that the one or more performance capabilities of a downstream device are less than the performance capabilities of the device, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the downstream device, including allocating fewer lanes in the PCIe bus for use by the device than would be allocated for the device if the allocating were performed in dependence upon the performance capabilities of the device.

2. The apparatus of claim 1 wherein determining a device type for the device coupled to the PCIe bus further comprises retrieving, from the device, vital product data (‘VPD’) for the device.

3. The apparatus of claim 1 wherein allocating the number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device further comprises deallocating one or more lanes in the PCIe bus for use by a second device.

4. A computer program product including a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:
determining performance capabilities of a device coupled to a Peripheral Component Interconnect Connect Interface Express (PCIe) bus, including:
retrieving, from a downstream device, performance capabilities of a downstream device by initiating performance tests with the downstream device, wherein the performance tests include ping operations directed to the downstream device that determine a response time of the downstream device;
maintaining a repository that associates various device types with performance ca s abilities of each of the various device types;
determining a device type for the device coupled to the PCIe bus;
retrieving, from the repository, performance capabilities of the device; and
determining whether one or more performance capabilities of a downstream device are less than the performance capabilities of the device coupled to the PCIe bus, wherein the downstream device is coupled to the device over a data communications channel other than the PCIe bus; and

allocating, in response to determining that the one or more performance capabilities of a downstream device are less than the performance capabilities of the device, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the downstream device, including allocating fewer lanes in the PCIe bus for use by the device than would be allocated for the device if the allocating were performed in dependence upon the performance capabilities of the device.

5. The computer program product of claim 4 wherein determining a device type for the device coupled to the PCIe bus further comprises retrieving, from the device, vital product data (‘VPD’) for the device.

6. The computer program product of claim 4 wherein allocating the number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device further comprises deallocating one or more lanes in the PCIe bus for use by a second device.

7. The computer program product of claim 4 wherein the computer readable medium comprises a computer readable storage medium.

8. A method comprising:
determining performance capabilities of a device coupled to a Peripheral Component Interconnect Connect Interface Express (PCIe) bus, including:
retrieving, from a downstream device, performance capabilities of a downstream device by initiating performance tests with the downstream device, wherein the performance tests include ping operations directed to the downstream device that determine a response time of the downstream device;
maintaining a repository that associates various device types with performance capabilities of each of the various device types;
determining a device type for the device coupled to the PCIe bus;
retrieving, from the repository, performance capabilities of the device; and
determining whether one or more performance capabilities of a downstream device are less than the performance capabilities of the device coupled to the PCIe bus, wherein the downstream device is coupled to the device over a data communications channel other than the PCIe bus; and

allocating, in response to determining that the one or more performance capabilities of a downstream device are less than the performance capabilities of the device, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the downstream device, including allocating fewer lanes in the PCIe bus for use by the device than would be allocated for the device if the allocating were performed in dependence upon the performance capabilities of the device.

9. The method of claim 8 wherein determining a device type for the device coupled to the PCIe bus further comprises retrieving, from the device, vital product data (‘VPD’) for the device.

10. The method of claim 8 wherein allocating the number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device further comprises deallocating one or more lanes in the PCIe bus for use by a second device.

11. The method of claim 1 wherein the allocating the number of lanes includes allocating a number of lanes equal to a maximum performance capability of the downstream device.

12. The method of claim 1 further comprising allocating, in response to determining that the one or more performance capabilities of a downstream device are more than the performance capabilities of the device, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device.

Assignees

• Lenovo Entpr Solutions Singapore Pte Ltd

Inventors

• Jacobson Steven C
• Nguyen Loc X
• Remis Luke D
• Tennant Timothy R

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title