Translation of input/output addresses to memory addresses

Patent metadata

Field	Value
Publication number	US-9626298-B2
Application number	US-201314093609-A
Country	US
Kind code	B2
Filing date	Dec 2, 2013
Priority date	Jun 23, 2010
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

First claim

What is claimed is:

1. A computer system for translating addresses in a computing environment, said computer system comprising:
an adapter; and
a hardware unit coupled to the adapter, wherein the hardware unit is configured to perform a method, the method comprising:
obtaining an address from the adapter to be translated by traversing a number of levels of address translation tables, the address to be translated by traversing the number of levels of address translation tables comprising a plurality of bits, the plurality of bits comprising a first portion of bits and a second portion of bits; and
converting the address to a memory address usable in accessing memory of the computing environment, the converting ignoring the first portion of bits in traversing the number of levels of address translation tables and using the second portion of bits in traversing the number of levels of address translation tables to obtain address information from one or more levels of address translation tables to obtain the memory address, wherein the traversing the number of levels of address translation tables includes using one part of the second portion of bits to locate an entry in one address translation table at one level of address translation tables, and using information in that entry to select another table to be used in obtaining the address information.

2. The computer system of claim 1 , wherein the first portion of bits comprises high order bits of the address and the second portion of bits comprises low order bits of the address, the low order bits determined based on a size of an assigned address space that includes the memory address.

3. The computer system of claim 1 , wherein the number of levels of address translation tables is based on at least one of a size of an assigned address space that includes the memory address, a size of one or more address translation tables to be used in the converting, and a size of a unit of memory accessed by the memory address.

4. The computer system of claim 1 , wherein the converting comprises selecting an address translation table to be used to convert the address, the selecting using a pointer in a device table entry used in the converting.

5. The computer system of claim 4 , wherein the method further comprises locating the device table entry, the locating using at least one of a requestor identifier of the adapter issuing a request that includes the address to be translated or a portion of the address.

6. The computer system of claim 4 , wherein the method further comprises determining a format of the selected address translation table, the determining using a format field of the device table entry.

7. The computer system of claim 1 , wherein the method further comprises:
receiving an address range value that indicates an address range of permitted addresses; and
validating the address using at least the first portion of bits and the received address range value.

8. The computer system of claim 7 , wherein the address range is defined by at least one of a base field and a limit field of a device table entry to validate the address.

9. The computer system of claim 8 , wherein the validating the address comprises permitting execution based on determining that the at least first portion of bits are within a range of corresponding bits of the address range, wherein the corresponding bits of the address range are not all 0's.

10. The computer system of claim 1 , wherein the adapter comprises a function, the function comprising a Peripheral Component Interconnect function.

11. A computer program product for translating addresses in a computing environment, said computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
obtaining an address from an adapter to be translated by traversing a number of levels of address translation tables, the address to be translated by traversing the number of levels of address translation tables comprising a plurality of bits, the plurality of bits comprising a first portion of bits and a second portion of bits; and
converting the address to a memory address usable in accessing memory of the computing environment, the converting ignoring the first portion of bits in traversing the number of levels of address translation tables and using the second portion of bits in traversing the number of levels of address translation tables to obtain address information from one or more levels of address translation tables to obtain the memory address, wherein the traversing the number of levels of address translation tables includes using one part of the second portion of bits to locate an entry in one address translation table at one level of address translation tables, and using information in that entry to select another table to be used in obtaining the address information.

12. The computer program product of claim 11 , wherein the first portion of bits comprises high order bits of the address and the second portion of bits comprises low order bits of the address, the low order bits determined based on a size of an assigned address space that includes the memory address.

13. The computer program product of claim 11 , wherein the number of levels of address translation tables is based on at least one of a size of an assigned address space that includes the memory address, a size of one or more address translation tables to be used in the converting, and a size of a unit of memory accessed by the memory address.

14. The computer program product of claim 11 , wherein the converting comprises selecting an address translation table to be used to convert the address, the selecting using a pointer in a device table entry used in the converting.

15. The computer program product of claim 14 , wherein the method further comprises locating the device table entry, the locating using at least one of a requestor identifier of the adapter issuing a request that includes the address to be translated or a portion of the address.

16. The computer program product of claim 14 , wherein the method further comprises determining a format of the selected address translation table, the determining using a format field of the device table entry.

17. The computer program product of claim 11 , wherein the method further comprises:
receiving an address range value that indicates an address range of permitted addresses; and
validating the address using at least the first portion of bits and the received address range value, wherein the address range is defined by at least one of a base field and a limit field of a device table entry to validate the address, and wherein the validating the address comprises permitting execution based on determining that the at least first portion of bits are within a range of corresponding bits of the address range, wherein the corresponding bits of the address range are not all 0's.

18. A method of translating addresses in a computing environment, said method comprising:
obtaining, by a hardware unit, an address from an adapter to be translated by traversing a number of levels of address translation tables, the address to be translated by traversing the number of levels of address translation tables comprising a plurality of bits, the plurality of bits comprising a first portion of bits and a second portion of bits; and
converting the address to a memory address usable in accessing memory of the computing environment, the converting ignoring the first po

Assignees

• IBM

Inventors

• Craddock David
• Gregg Thomas A
• Greiner Dan F
• Lais Eric N

Classifications

• G06F9/355

  Indexed addressing · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F12/0292 Primary

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F2212/206

  Memory mapped I/O · CPC title

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title