Memory tile access and selection patterns

Patent metadata

Field	Value
Publication number	US-9626292-B2
Application number	US-201615194154-A
Country	US
Kind code	B2
Filing date	Jun 27, 2016
Priority date	Jun 17, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.

First claim

What is claimed is:

1. An apparatus comprising:
a controller configured to:
switch a plurality of switching devices to select a storage component of a plurality of memory tiles according to a memory address associated with at least a digit line conductor and an access line conductor for the storage component, each memory tile of the plurality of memory tiles comprising an array of uniquely addressable storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors, and
determine a next memory address to select with the plurality of switching devices based at least partly on a previously selected memory address; and

a memory configured to store the next memory address,
wherein the controller is configured to consecutively select at least two or more storage components of a memory tile of the plurality of memory tiles in a consecutive manner before selecting the storage components of a different memory tile of the plurality of memory tiles.

2. The apparatus of claim 1 , wherein the controller is further configured to determine the next memory address using a tile mapper, the tile mapper configured to map an input address to an output address according to a tile access pattern.

3. The apparatus of claim 2 , wherein the more than two selected storage components of the memory tile include a first storage component, a second storage component, and a third storage component, the first, second, and third storage components having different corresponding digit line conductors and different corresponding access line conductors.

4. The apparatus of claim 3 , wherein the first, second, and third storage components are non-adjacent to each other in the array of uniquely addressable storage components of the memory tile.

5. The apparatus of claim 3 , wherein the first storage component is separated from the second storage component by a distance and the second storage component is separated from the third storage component by the distance.

6. The apparatus of claim 1 , wherein the controller is further configured to determine the next memory address according to an address stored in a look-up table.

7. A method of accessing a memory device, the method comprising:
determining a memory address of a memory location having a corresponding digit line conductor and a corresponding access line conductor in a memory tile based at least in part on a previously selected memory address in the memory tile; and
selecting the corresponding digit line conductor and the corresponding access line conductor of the determined memory address to access the memory location of the memory tile,
wherein the corresponding digit line conductor and the corresponding access line conductor of the determined memory address differ from a digit line conductor and from a access line conductor of the previously selected memory address in the memory tile.

8. The method of claim 7 , wherein selecting the corresponding digit line conductor and the corresponding access line conductor of the determined memory address occurs before a threshold recovery time associated with the previously selected memory address.

9. The method of claim 7 , wherein determining the memory address of the memory location comprises determining the memory address using a mapper or a look-up table.

10. The method of claim 7 , wherein determining the memory address of the memory location comprises determining the memory address along a diagonal in the memory tile from the previously selected memory address.

11. The method of claim 7 , wherein selecting the corresponding digit line conductor and the corresponding access line conductor of the determined memory address occurs before selecting a memory location of a second memory tile.

12. The method of claim 7 , wherein determining the memory address of the memory location is based at least in part on a distance from the memory location to the previously selected memory address.

13. The method of claim 12 , wherein determining the memory address of the memory location comprises:
identifying a range of memory locations based at least in part on a selection pattern; and
selecting the memory address of at least one memory location of the identified range of memory locations.

14. The method of claim 7 , further comprising:
assigning one or more memory locations to a group; and
selecting the one or more memory locations before selecting a different memory location assigned to a different group based at least in part on the assigning.

15. A memory device comprising:
a memory tile including an array of memory cells at intersections of a plurality of digit line conductors and a plurality of access line conductors; and
a controller operable to select a memory cell of the array of memory cells according to a memory address for the memory cell and determine a next memory address for selection based at least in part on a previously selected memory address, the memory address for the memory cell being associated with a digit line conductor of the plurality of digit line conductors and an access line conductor of the plurality of access line conductors,
wherein the controller is operable to consecutively select two or more memory cells of the memory tile before selecting a memory cell of a different memory tile.

16. The memory device of claim 15 , wherein the controller is further operable to determine the next memory address based at least in part on a number of access line conductors or a number of digit line conductors between the previously selected memory address and the next memory address.

17. The memory device of claim 15 , wherein the controller is further operable to:
determine a set of memory addresses based at least in part on a tile access pattern; and
select a memory address from the set of memory addresses based at least in part on a location of the previously selected memory address associated with the tile access pattern.

18. The memory device of claim 15 , wherein the controller is further operable to:
assign one or more memory cells of the memory tile to a group; and
select the one or more memory cells of the group before selecting a different memory cell assigned to a different group based on a location associated with at least one of the one or more memory cells in the group.

19. The memory device of claim 15 , wherein the controller is further operable to:
select the memory cell before expiration of a threshold recovery time associated with a selection of the previously selected memory address.

20. The memory device of claim 15 , wherein the controller is further operable to:
select a second memory cell after expiration of a threshold recovery time associated with a selection of a previously selected memory cell, wherein the previously selected memory cell and the second memory cell are associated with a same digit line conductor or a same access line conductor.

Assignees

• Micron Technology Inc

Inventors

• Castro Hernan A
• Tedrow Kerry Dean
• Wu Jack Chinho

Classifications

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C8/10 Primary

  Decoders · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0635

  by changing the path, e.g. traffic rerouting, path reconfiguration · CPC title