Debug method and device for handling exceptions and interrupts

Patent metadata

Field	Value
Publication number	US-9626280-B2
Application number	US-201313932189-A
Country	US
Kind code	B2
Filing date	Jul 1, 2013
Priority date	Jul 1, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.

First claim

What is claimed is:

1. A method comprising:
in response to an occurrence of an exception/interrupt, executing an exception/interrupt handler;
determining if a predicted return address of a Return From Exception Or Interrupt (RFEOI) instruction of the exception/interrupt handler results in a match or a mismatch with an actual return address of the RFEOI instruction; and
generating a first trace address message identifying the actual return address in response to determining the mismatch, otherwise, not generating the trace address message identifying the actual return address in response to determining match.

2. The method of claim 1 , wherein the predicted return address is based upon an address of an exceptional instruction.

3. The method of claim 2 , wherein the predicted address is the same as the address of the exceptional instruction that was being executed.

4. The method of claim 2 , wherein the predicted address is an address of an instruction after the exceptional instruction.

5. The method of claim 1 further comprising:
prior to determining the match or mismatch, generating a second trace address message in response to occurrence of the exception/interrupt, the second trace address message comprising information from which the predicted return address can be determined.

6. The method of claim 5 , wherein the information includes an indicator whether execution of the exceptional instruction was completed.

7. The method of claim 6 , wherein in response to the instruction type indicating the exceptional instruction is of a first type the predicted address has a first value, and in response to the instruction type indicating the exceptional instruction is of a second type the predicted address has a second value.

8. The method of claim 1 further comprising:
in response to the exception/interrupt, generating a trace history message having a first indicator corresponding to the exception/interrupt, wherein the trace history message is generated independent as to a fullness of a history buffer comprising the first indicator.

9. The method of claim 8 , wherein the generated trace history message further comprises a second indicator corresponding to execution of a branch instruction.

10. The method of claim 1 further comprising:
in response to the exception/interrupt, adding a first indicator corresponding to the exception/interrupt to a history buffer, wherein a trace history message comprising the first indicator is generated in response to the history buffer meeting a fullness criteria.

11. The method of claim 1 further comprising:
asserting a history indicator in response to the RFEOI instruction being executed, wherein the history indicator is asserted independent of determining match or mismatch.

12. The method of claim 1 , wherein no history information is maintained indicating whether the match or mismatch was detected.

13. A data processing system comprising:
a data processor core; and
a debug module coupled to the data processor core, the debug module configured
to determine if a predicted return address of an Return From Exception or Return from Interrupt (RFEOI) instruction results in a match or a mismatch with an actual return address of the RFEOI instruction, and
to send a trace address message identifying the actual return address in response to determining mismatch, otherwise, not sending the trace address message in response to determining match.

14. The data processing system of claim 13 , wherein debug module determines the predicted return address based upon an address of an exceptional instruction.

15. The data processing system of claim 13 , wherein the debug module is further configured to, prior to determining the match or mismatch, generate a second trace address message in response to occurrence of an exception/interrupt, the second trace address message comprising information from which the predicted return address can be determined.

16. The data processing system of claim 15 , wherein the information includes an instruction type of an exceptional instruction.

17. The data processing system of claim 13 , wherein the debug module is further configured to, in response to an exception/interrupt corresponding the RFEOI instruction, generate a trace history message having a first indicator corresponding to the exception/interrupt instruction independent as to fullness of a trace history buffer comprising the first indicator.

18. The data processing system of claim 13 , wherein the debug module is further configured to, in response to an exception/interrupt corresponding the RFEOI instruction, add a first indicator corresponding to the exception/interrupt to a history buffer, and to generate a trace history message based upon the history buffer in response to the history buffer meeting a fullness criteria.

19. A method comprising:
determining that a Return From Exception Or Interrupt (RFEOI) instruction has been executed at a data processor;
in response to determining that a first trace address message has been received corresponding to the RFEOI instruction, reporting instruction flow subsequent to the RFEOI instruction as continuing at a first return address provided as part of the first trace address message, otherwise, in response to determining that a first trace address message has not been received corresponding to the RFEOI instruction, reporting instruction flow subsequent to the RFEOI instruction as continuing at a second return address that is based upon information received prior to execution of the RFEOI instruction.

20. The method of claim 19 further comprising:
receiving a second trace address message providing the second return address, the second trace address message received in response to an occurrence of an exception/interrupt event, and the second return address based upon the address of an exceptional instruction.

Assignees

• Ehrlich Robert N
• Mcgowan Robert A
• Schinzler Michael B
• Nxp Usa Inc

Inventors

• Ehrlich Robert N
• Mcgowan Robert A
• Schinzler Michael B

Classifications

• G06F11/3636 Primary

  by tracing the execution of the program · CPC title

• G06F9/323

  for indirect branch instructions · CPC title

• G06F9/30054

  Unconditional branch instructions · CPC title