Instruction and logic for tracking access to monitored regions

Patent metadata

Field	Value
Publication number	US-9626274-B2
Application number	US-201414580676-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.

First claim

What is claimed is:

1. A processor, comprising:
a front end including a decoder, the decoder including circuitry to receive a tracking instruction available on the processor, the tracking instruction executable to enable tracking of execution of instructions in a region of memory, and the tracking instruction to define an address range of the region;
a retirement unit including circuitry to retire the tracking instruction, a first candidate instruction, and a second candidate instruction; and
a performance monitoring unit, including circuitry to:
filter instructions based upon the address range;
determine that the first candidate instruction is associated with an entrance to the address range;
determine that the second candidate instruction is associated with an exit to the address range; and
generate an alert based upon the association of the first candidate instruction with the entrance to the address range and upon the association of the second candidate instruction with the exit to the address range.

2. The processor of claim 1 , wherein the performance monitoring unit further includes circuitry to:
increment a counter to indicate entrances to the address range based upon the determination that the first candidate instruction is associated with the entrance to the address range;
compare the counter to a threshold number of entrances; and
generate the alert further based upon the counter greater than the threshold number of entrances.

3. The processor of claim 1 , wherein the performance monitoring unit further includes circuitry to:
compare a process of the first candidate instruction to an identified process to be tracked; and
generate the alert further based upon the process of the first candidate associated with the identified process to be tracked.

4. The processor of claim 1 , wherein the performance monitoring unit further includes circuitry to:
compare a privilege of the first candidate instruction to an identified privilege level to be tracked; and
generate the alert further based upon a match of the privilege level of the first candidate with the identified privilege level to be tracked.

5. The processor of claim 1 , further comprising a processor trace unit including circuitry to define the address range to be tracked to the performance monitoring unit.

6. The processor of claim 1 , wherein the performance monitoring unit, further includes circuitry to determine that the region has been executed based upon the association of the first candidate instruction with the entrance to the address range and upon the association of the second candidate instruction with the exit to the address range.

7. The processor of claim 1 , wherein:
the tracking instruction includes a designation of N entrance and exit combinations; and
the performance monitoring unit further includes circuitry to generate an alert on every Nth determined entrance and exit combinations.

8. A method comprising, within a hardware processor:
receiving a tracking instruction available on the processor, the tracking instruction executable to enable tracking of execution of instructions in a region of memory, and the tracking instruction to define an address range of the region;
retiring the tracking instruction, a first candidate instruction, and a second candidate instruction;
filtering instructions based upon the address range;
determining that the first candidate instruction is associated with an entrance to the address range;
determining that the second candidate instruction is associated with an exit to the address range; and
generating an alert based upon the association of the first candidate instruction with the entrance to the address range and upon the association of the second candidate instruction with the exit to the address range.

9. The method of claim 8 , further comprising:
incrementing counter to indicate entrances to the address range based upon the determination that the first candidate instruction is associated with the entrance to the address range;
comparing the counter to a threshold number of entrances; and
generating the alert further based upon the counter exceeding the threshold number of entrances.

10. The method of claim 8 , further comprising:
comparing a process of the first candidate instruction to an identified process to be tracked; and
generating the alert further based upon the process of the first candidate associated with the identified process to be tracked.

11. The method of claim 8 , further comprising:
comparing a privilege of the first candidate instruction to an identified privilege level to be tracked; and
generating the alert further based upon a match of the privilege level of the first candidate with the identified privilege level to be tracked.

12. The method of claim 8 , further comprising defining the address range with a processor trace unit to filtering logic of a performance monitoring unit for filtering the instructions.

13. The method of claim 8 , further comprising determining that the region has been executed based upon the association of the first candidate instruction with the entrance to the address range and upon the association of the second candidate instruction with the exit to the address range.

14. A system comprising:
a front end including a decoder, the decoder including circuitry to receive a tracking instruction available on the processor, the tracking instruction executable to enable tracking of execution of a region of memory, and the tracking instruction to define an address range of the region;
a retirement unit including circuitry to retire the tracking instruction, a first candidate instruction, and a second candidate instruction; and
a performance monitoring unit, including circuitry to:
filter instructions based upon the address range;
determine that the first candidate instruction is associated with an entrance to the address range;
determine that the second candidate instruction is associated with an exit to the address range; and
based upon the association of the first candidate instruction with the entrance to the address range and upon the association of the second candidate instruction with the exit to the address range, generate an alert.

15. The system of claim 14 , wherein the performance monitoring unit further includes circuitry to:
increment a counter to indicate entrances to the address range based upon the determination that the first candidate instruction is associated with the entrance to the address range;
compare the counter to a threshold number of entrances; and
generate the alert further based upon the counter exceeding the threshold number of entrances.

16. The system of claim 14 , wherein the performance monitoring unit further includes circuitry to:
compare a process of the first candidate instruction to an identified process to be tracked; and
generate the alert further based upon the process of the first candidate associated with the identified process to be tracked.

17. The system of claim 14 , wherein the performance monitoring unit further includes circuitry to:
compare a privilege of the first candidate instruction to an identified privilege level to be tracked; and
generate the alert further based upon a match of the privilege level of the first candidate with the identified privilege level to be tracked.

18. The system of claim 14 , further comprising a processor trace unit including circuitry to define the address range to be tracked to the performance monitoring unit.

19. The system of

Assignees

• Yasin Ahmad
• Chabukswar Rajshree A
• Levy Ofer
• Chynoweth Michael W
• Hewett Charlie J
• Intel Corp

Inventors

• Yasin Ahmad
• Chabukswar Rajshree A
• Levy Ofer
• Chynoweth Michael W
• Hewett Charlie J

Classifications

• G06F2201/81

  Threshold · CPC title

• G06F11/3471 Primary

  Address tracing · CPC title

• G06F11/3466

  Performance evaluation by tracing or monitoring · CPC title

• G06F2201/88

  Monitoring involving counting · CPC title

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title