Test generation using expected mode of the target hardware device

Patent metadata

Field	Value
Publication number	US-9626267-B2
Application number	US-201514610297-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jan 30, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be executed when operating in a first mode of operation; in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to a second mode; and generating a second set of instructions for the hardware component, that are to be executed when operating in the second mode of operation. The generation of instructions comprises determining the expected mode and generating instructions in accordance with the expected mode of the hardware component. The generation is performed without having an expected full state of the hardware component.

First claim

What is claimed is:

1. A method for testing a hardware component capable of switching between at least two modes of operation, comprising:
setting an expected mode of the hardware component to a first mode;
parsing a test template containing a plurality of template statements of tests to be performed on the hardware component, wherein at least one template statement is a marker statement indicating a request to change a mode of operation of the hardware component; and
generating instructions for the hardware components based on one or more parsed template statements, wherein said generating instructions comprises:
generating a first set of instructions for the hardware component, wherein the first set of instructions is to be executed by the hardware component when operating in the first mode of operation;
in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to the second mode; and
generating a second set of instructions for the hardware component, wherein the second set of instructions is to be executed by the hardware component when operating in the second mode of operation;
wherein said generating the first set and generating the second set comprise: determining the expected mode of the hardware component and generating instructions in accordance with the expected mode of the hardware component;
wherein said generating the first set and generating the second set are performed without having an expected full state of the hardware component.

2. The method of claim 1 , wherein the marker statement is a dedicated instruction of the hardware component to change its mode of operation.

3. The method of claim 1 , wherein the marker statement is a system call, wherein the system call is not configured to change the mode of operation of the hardware component.

4. The method of claim 1 , wherein the marker statement is an illegal instruction.

5. The method of claim 1 , wherein the at least two modes of operation of the hardware component are different orderings of data storage in memory.

6. The method of claim 1 , wherein the at least two modes of operation of the hardware component are different mappings of memory addresses.

7. The method of claim 1 , wherein the at least two modes of operation of the hardware component are different instruction sets supported by the hardware component.

8. The method of claim 1 , further comprising processing the generated first and second set of instructions by a debugging tool, wherein each set is processed in accordance with the respective expected mode of the hardware component as determined based on the marker statement.

9. A computerized apparatus for testing a hardware component capable of switching between at least two modes of operation, wherein said computerized apparatus comprises a processor, wherein said computerized apparatus comprising:
a test template parsing component for parsing a test template containing a plurality of template statements of tests to be performed on the hardware component, wherein at least one template statement is a marker statement indicating a request to change a mode of operation of the hardware component;
an expected mode determination component for determining an expected mode of the hardware component, wherein said expected mode determination component is configured to determine the expected mode based on the marker statement, wherein the expected mode is determined without having an expected full state of the hardware component;
a test generator component for generating a set of instructions to be executed by the hardware component under test based on a template statement parsed by said test template parsing component, said test generator is adapted to generate the instructions in accordance with an expected mode of operation of the hardware component, wherein, responsive to a parsed template statement being a marker statement, said test generator is configured to generate an intermediary set of instructions to cause the hardware component to change the mode of operation and to update the expected mode of the hardware component accordingly; and
a checking component for verifying correctness of data resulting from executing a generated set of instructions by the hardware component, wherein said checking component verifies the results in accordance with the expected mode of the hardware component during execution.

10. The computerized apparatus of claim 9 , wherein the marker statement is a dedicated instruction of the hardware component to change its mode of operation.

11. The computerized apparatus of claim 9 , wherein the marker statement is a system call.

12. The computerized apparatus of claim 9 , wherein the marker statement is an illegal instruction.

13. The computerized apparatus of claim 9 , wherein the at least two modes of operation of the hardware component are different orderings of data storage in memory.

14. The computerized apparatus of claim 9 , wherein the at least two modes of operation of the hardware component are different mappings of memory addresses.

15. The computerized apparatus of claim 9 , wherein the at least two modes of operation of the hardware component are different instruction sets supported by the hardware component.

16. The computerized apparatus of claim 9 , further comprising a debugging tool configured to process the generated first and second set of instructions, wherein each set is processed in accordance with the respective expected mode of the hardware component, wherein said debugging tool is operatively coupled to said expected mode determination component.

17. The computerized apparatus of claim 9 , wherein said expected mode determination component is configured to operate without making use of a reference model of the hardware component.

18. The computerized apparatus of claim 9 , wherein said expected mode determination component is configured to determine an expected mode of operation of the hardware component without having an expected value of a register of the hardware component.

19. The computerized apparatus of claim 9 , wherein said expected mode determination component is configured to determine the expected mode based on the marker statement by parsing a stream of instructions which are being executed by the hardware component and identifying the intermediary set of instructions within the stream of instructions.

20. A computer program product comprising a non-transitory computer readable storage medium retaining program instructions, which program instructions when read by a processor, cause the processor to perform a method for testing a hardware component capable of switching between at least two modes of operation, wherein the method comprising:
setting an expected mode of the hardware component to a first mode;
parsing a test template containing a plurality of template statements of tests to be performed on the hardware component, wherein at least one template statement is a marker statement indicating a request to change a mode of operation of the hardware component; and
generating instructions for the hardware components based on one or more parsed template statements, wherein said generating instructions comprises:
generating a first set of instructions for the hardware component, wherein the first set of instructions is to be

Assignees

• Samsung Ltd
• IBM

Inventors

• Park Sung-Boem
• Nahir Amir
• Sokhin Vitali
• Kadry Wisam
• Park Jin Sung
• Cho Ara

Classifications

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title