Efficiency of cycle-reproducible debug processes in a multi-core environment

Patent metadata

Field	Value
Publication number	US-9626265-B2
Application number	US-201514753324-A
Country	US
Kind code	B2
Filing date	Jun 29, 2015
Priority date	Jun 29, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.

First claim

What is claimed is:

1. A method for improving efficiency of cycle-reproducible debug in a multi-core environment, the method comprising:
executing, by one or more computer processors, an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds;
determining, by one or more computer processors, a seed from the one or more different seeds that locates a fail-condition;
responsive to determining a seed from the one or more different seeds that locates the fail condition, determining, by one or more computer processors, an upper bound and a lower bound of the fail-condition;
determining, by one or more computer processors, whether the fail-condition has occurred within a range of cycles executed on each of the one or more cores;
responsive to a determination that the fail-condition has occurred within the range of cycles executed by at least one of the one or more cores, determining, by one or more computer processors, a lowest cycle count in the at least one of the one or more cores where the fail-condition has occurred as an upper bound;
responsive to a determination that the fail-condition has not occurred within the range of cycles executed by at least one of the one or more cores, resetting, by one or more computer processors, each of the one or more cores with a higher stopping cycle;
determining, by one or more computer processors, an exact cycle where the fail-condition occurs; and
constructing, by one or more computer processors, a multi-cycle trace for the fail-condition.

2. The method of claim 1 , wherein executing an exerciser image on one or more cores, further comprises:
presetting, by one or more computer processors, each of the one or more cores with the one or more different seeds, wherein the one or more different seeds are at least one of: a pseudo random value or a binary value; and
evaluating, by one or more computer processors, the one or more different seeds for each of the one or more cores concurrently.

3. The method of claim 1 , wherein determining an upper bound and a lower bound of a fail-condition, further comprises:
executing, by one or more computer processors, the exerciser image with the seed on each of the one or more cores for a range of cycles, wherein each of the one or more cores is set to stop at a different cycle within the range of cycles; and
searching, by one or more computer processors, from an initial cycle at the beginning of a test execution run where the fail-condition does not exist to a subsequent cycle of a test execution run where the fail-condition exists.

4. The method of claim 1 , wherein determining an exact cycle where the fail-condition occurs, further comprises:
performing, by one or more computer processors, a plurality of distributed searches for the fail-condition across each of the one or more cores, wherein performing the plurality of distributed searches includes distributing a number of cycles between the upper bound and the lower bound across each of the one or more cores.

5. The method of claim 1 , wherein constructing a multi-cycle trace for the fail-condition, further comprises:
performing, by one or more computer processors, one test execution per-cycle, including the exact cycle where the fail condition occurred; and
extracting, by one or more computer processors, data from one or more cycles preceding the exact cycle where the fail-condition occurred, data from the exact cycle where the fail-condition occurred, and data from one or more cycles subsequent to the exact cycle where the fail-condition occurred.

6. The method of claim 5 further comprises:
aggregating, by one or more computer processors, test data collected from a plurality of test executions.

7. A computer program product for improving efficiency of cycle-reproducible debug in a multi-core environment, the computer program product comprising:
one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising:
program instructions to execute an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds;
program instructions to determine a seed from the one or more different seeds that locates a fail-condition;
responsive to determining a seed from the one or more different seeds that locates the fail condition, program instructions to determine an upper bound and a lower bound of the fail-condition;
program instructions to determine whether the fail-condition has occurred within a range of cycles executed on each of the one or more cores;
responsive to a determination that the fail-condition has occurred within the range of cycles executed by at least one of the one or more cores, program instructions to determine a lowest cycle count in the at least one of the one or more cores where the fail-condition has occurred as an upper bound;
responsive to a determination that the fail-condition has not occurred within the range of cycles executed by at least one of the one or more cores, program instructions to reset each of the one or more cores with a higher stopping cycle;
program instructions to determine an exact cycle where the fail-condition occurs; and
program instructions to construct a multi-cycle trace for the fail-condition.

8. The computer program product of claim 7 , wherein program instructions to execute an exerciser image on one or more cores, further comprises:
program instructions to preset each of the one or more cores with the one or more different seeds, wherein the one or more different seeds are at least one of: a pseudo random value or a binary value; and
program instructions to evaluate the one or more different seeds for each of the one or more cores concurrently.

9. The computer program product of claim 7 , wherein program instructions to determining an upper bound and a lower bound of a fail-condition, further comprises:
program instructions to execute the exerciser image with the seed on each of the one or more cores for a range of cycles, wherein each of the one or more cores is set to stop at a different cycle within the range of cycles; and
program instructions to search from an initial cycle at the beginning of a test execution run where the fail-condition does not exist to a subsequent cycle of a test execution run where the fail-condition exists.

10. The computer program product of claim 7 , wherein program instructions to determine an exact cycle where the fail-condition occurs, further comprises:
program instructions to perform a plurality of distributed searches for the fail-condition across each of the one or more cores, wherein performing the plurality of distributed searches includes distributing a number of cycles between the upper bound and the lower bound across each of the one or more cores.

11. The computer program product of claim 7 , wherein program instructions to construct a multi-cycle trace for the fail-condition, further comprises:
program instructions to perform one test execution per-cycle, including the exact cycle where the fail condition occurred; and
program instructions to extract data from one or more cycles preceding the exact cycle where the fail-condition occurred, data from the exact cycle where the fail-condition occurred, and data from one or more cycles subsequent to the exact cycle where the fail-condition occurred.

12. The computer program product of claim 11 further comprises:
program instructions to aggregate test data collected from a plurality of test executions.

13. A computer system for improving efficiency of cycle-reproducible de

Assignees

• IBM

Inventors

• Klazynski James N
• Nahir Amir

Classifications

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F11/26 Primary

  Functional testing · CPC title

• G06F11/2242 Primary

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title

• G06F11/362

  Debugging of software · CPC title

• G01R31/31705

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title