Shaped register file reads

Patent metadata

Field	Value
Publication number	US-9626191-B2
Application number	US-201113335868-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

One embodiment of the present invention sets forth a technique for performing a shaped access of a register file that includes a set of N registers, wherein N is greater than or equal to two. The technique involves, for at least one thread included in a group of threads, receiving a request to access a first amount of data from each register in the set of N registers, and configuring a crossbar to allow the at least one thread to access the first amount of data from each register in the set of N registers.

First claim

What is claimed is:

1. A computer-implemented method for performing access of a register file that includes a set of N registers, wherein N is greater than or equal to two, the method comprising:
from each thread included in a plurality of threads executed by a processor, receiving a request to access a first amount of data from each register in the set of N registers; and
configuring a crossbar, connecting the register file with the processor, to allow the plurality of threads to access data from each register in the set of N registers, and to allow each thread of the plurality of threads to access the first amount of data from each register in the set of N registers in a single clock cycle.

2. The computer-implemented method of claim 1 , wherein the register file comprises a plurality of memory banks, and each register in the set of N registers resides in a different memory bank.

3. The computer-implemented method of claim 1 , wherein, at each clock cycle, each thread accesses the first amount of data from either:
each register in the set of N registers to produce an access operation comprising N accesses of the first amount of data;
each register in N/2 aligned pairs of sequential registers to produce an access operation comprising N/2 accesses of twice the first amount of data; or
each register in N/4 aligned quads of sequential registers to produce an access operation comprising N/4 accesses of four times the first amount of data.

4. The computer-implemented method of claim 1 , wherein the set of N registers includes N/2 aligned pairs of sequential registers, and each thread accesses the first amount of data from each register in each aligned pair of sequential registers in a single clock cycle to produce a shaped access operation comprising N/2 accesses of twice the first amount of data.

5. The computer-implemented method of claim 1 , wherein the set of N registers includes N/4 aligned quads of sequential registers, and each thread accesses the first amount of data from each register in each aligned quad of sequential registers in a single clock cycle to produce a shaped access operation comprising N/4 accesses of four times the first amount of data.

6. The computer-implemented method of claim 1 , wherein the plurality of threads comprises a subset of a second group of threads and includes either a sequential lower half of the threads included in the second group of threads or a sequential upper half of the threads included in the second group of threads.

7. The computer-implemented method of claim 1 , wherein each thread accesses the first amount of data by either reading the first amount of data from each register in the set of N registers or writing the first amount of data to each register in the set of N registers.

8. The computer-implemented method of claim 1 , wherein the first amount of data comprises 32-bits of data.

9. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform access of a register file that includes a set of N registers, wherein N is greater than or equal to two, by performing the steps of:
from each thread included in a plurality of threads executed by a processor, receiving a request to access a first amount of data from each register in the set of N registers; and
configuring a crossbar, connecting the register file with the processor, to allow the plurality of threads to access data from each register in the set of N registers, and to allow each thread of the plurality of threads to access the first amount of data from each register in the set of N registers in a single clock cycle.

10. The non-transitory computer-readable storage medium of claim 9 , wherein the register file comprises a plurality of memory banks, and each register in the set of N registers resides in a different memory bank.

11. The non-transitory computer-readable storage medium of claim 9 , wherein, at each clock cycle, each thread accesses the first amount of data from either:
each register in the set of N registers to produce an access operation comprising N accesses of the first amount of data;
each register in N/2 aligned pairs of sequential registers to produce an access operation comprising N/2 accesses of twice the first amount of data; or
each register in N/4 aligned quads of sequential registers to produce an access operation comprising N/4 accesses of four times the first amount of data.

12. The non-transitory computer-readable storage medium of claim 9 , wherein the set of N registers includes N/2 aligned pairs of sequential registers, and each thread accesses the first amount of data from each register in each aligned pair of sequential registers in a single clock cycle to produce a shaped access operation comprising N/2 accesses of twice the first amount of data.

13. The non-transitory computer-readable storage medium of claim 9 , wherein the set of N registers includes N/4 aligned quads of sequential registers, and each thread accesses the first amount of data from each register in each aligned quad of sequential registers in a single clock cycle to produce a shaped access operation comprising N/4 accesses of four times the first amount of data.

14. The non-transitory computer-readable storage medium of claim 9 , wherein the plurality of threads comprises a subset of a second group of threads and includes either a sequential lower half of the threads included in the second group of threads or a sequential upper half of the threads included in the second group of threads.

15. The non-transitory computer-readable storage medium of claim 9 , wherein each thread accesses the first amount of data by either reading the first amount of data from each register in the set of N registers or writing the first amount of data to each register in the set of N registers.

16. The non-transitory computer-readable storage medium of claim 9 , wherein the first amount of data comprises 32-bits of data.

17. A system for performing access of a register file that includes a set of N registers, wherein N is greater than or equal to two, the system comprising:
the register file;
a crossbar connecting the register file with a processor; and
the processor configured to:
from each thread included in a plurality of threads executed by a processor, receive a request to access a first amount of data from each register in the set of N registers; and
configure the crossbar to allow the plurality of threads to access data from each register in the set of N registers, and to allow each thread of the plurality of threads to access the first amount of data from each register in the set of N registers in a single clock cycle.

18. The system of claim 17 , wherein the register file comprises a plurality of memory banks, and each register in the set of N registers resides in a different memory bank.

19. The system of claim 17 , wherein, at each clock cycle, each thread accesses the first amount of data from either:
each register in the set of N registers to produce an access operation comprising N accesses of the first amount of data;
each register in N/2 aligned pairs of sequential registers to produce an access operation comprising N/2 accesses of twice the first amount of data; or
each register in N/4 aligned quads of sequential registers to produce an access operation comprising N/4 accesses of four times the first amount of data.

20. The system of claim 17 , wherein the set of N registers includes N/2 aligned pairs of sequential registers, a

Assignees

• Choquette Jack Hilaire
• Fetterman Michael
• Gadre Shirish
• Qiu Xiaogang
• Paranjape Omkar
• Rajendran Anjana
• Carlton Stewart Glenn
• Hill Eric Lyell
• Selvanesan Rajeshwaran
• Hahn Douglas J
• Nvidia Corp

Inventors

• Choquette Jack Hilaire
• Fetterman Michael
• Gadre Shirish
• Qiu Xiaogang
• Paranjape Omkar
• Rajendran Anjana
• Carlton Stewart Glenn
• Hill Eric Lyell
• Selvanesan Rajeshwaran
• Hahn Douglas J

Classifications

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title